Semiconductor memory device for suppressing noises occurring on bit and
word lines
    1.
    发明授权
    Semiconductor memory device for suppressing noises occurring on bit and word lines 失效
    用于抑制位和字线上发生的噪声的半导体存储器件

    公开(公告)号:US5418750A

    公开(公告)日:1995-05-23

    申请号:US200107

    申请日:1994-02-22

    摘要: A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups are regularly arranged in an opposite direction.

    摘要翻译: 半导体存储器件包括一系列存储器单元,分别连接到存储器单元的一系列位线,一系列读出放大器,连接到包括一系列位线的预定数量位线的相应位线组,用于读取 连接到位线组的位线的存储器单元的输出数据,位线组包括至少相邻的第一和第二位线组,分配在位线和读出放大器之间并具有门的至少第一和第二晶体管,用于 选择性地连接位线和读出放大器,以及一系列控制信号线,共同连接到连接到第一位线组的第一晶体管和连接到第二位线组的第二晶体管,使得连接到第一位线组的第一晶体管 第一位线组在一个方向上规则地排列,第二晶体管连接到第二位线组 第一位线组以相反的方向规则地布置。

    Voltage step-down circuit
    2.
    发明授权
    Voltage step-down circuit 有权
    电压降压电路

    公开(公告)号:US07795953B2

    公开(公告)日:2010-09-14

    申请号:US12051465

    申请日:2008-03-19

    IPC分类号: G05F1/10

    CPC分类号: G11C5/147

    摘要: According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.

    摘要翻译: 根据本发明的一个方面,提供了一种电压降压电路,包括:第一NMOS,其连接在通过在激活状态期间导通的PMOS的外部和内部电源电压之间,并且在待机状态期间断开 ; 连接在外部和内部电源电压之间的第二NMOS; 以及电流控制电路,其在将动作状态从活动状态切换到待机状态之后,将电流从内部电源电压吸收到地电平一段时间。

    DISCHARGE ORDER CONTROL CIRCUIT AND MEMORY DEVICE
    3.
    发明申请
    DISCHARGE ORDER CONTROL CIRCUIT AND MEMORY DEVICE 有权
    放电顺序控制电路和存储器件

    公开(公告)号:US20070274132A1

    公开(公告)日:2007-11-29

    申请号:US11671107

    申请日:2007-02-05

    IPC分类号: G11C11/22 G11C11/34

    CPC分类号: G11C5/14

    摘要: A discharge order control circuit includes a pool circuit, a delay circuit and a discharge unit to control a discharge order of internal power supplies. The pool circuit stores electric charges provided from a potential of an external power supply. The delay circuit operates on the electric charges stored in the pool circuit and delays a discharge signal generated when potential of the external power supply is lowered to a predetermined potential level. The delay circuit includes an inverter array having a plurality of stages each containing an inverter. The plurality of stages include a final stage that outputs the delayed discharge signal. Only the inverter of the final stage generates an RC delay. The discharge unit discharges a internal power supply included in the internal power supplies in response to the delayed discharge signal output from the inverter of the final stage of the inverter array.

    摘要翻译: 放电顺序控制电路包括用于控制内部电源的放电顺序的池电路,延迟电路和放电单元。 池电路存储从外部电源的电位提供的电荷。 延迟电路对存储在池电路中的电荷进行操作,并且当外部电源的电位降低到预定电位电平时,延迟产生的放电信号。 延迟电路包括具有多个级的逆变器阵列,每个级包含反相器。 多个级包括输出延迟放电信号的最后级。 只有最终级的逆变器产生RC延迟。 放电单元响应于从逆变器阵列的最后级的逆变器输出的延迟的放电信号,对包括在内部电源中的内部电源进行放电。

    Discharge order control circuit and memory device
    4.
    发明授权
    Discharge order control circuit and memory device 有权
    放电顺序控制电路和存储器件

    公开(公告)号:US07724581B2

    公开(公告)日:2010-05-25

    申请号:US11671107

    申请日:2007-02-05

    IPC分类号: G11C16/06 G05F3/02

    CPC分类号: G11C5/14

    摘要: A discharge order control circuit includes a pool circuit a delay circuit and a discharge unit to control a discharge order of internal power supplies. The pool circuit stores electric charges provided from a potential of an external power supply. The delay circuit operates on the electric charges stored in the pool circuit and delays a discharge signal generated when potential of the external power supply is lowered to a predetermined potential level. The delay circuit includes an inverter array having a plurality of stages each containing an inverter. The plurality of stages include a final stage that outputs the delayed discharge signal. Only the inverter of the final stage generates an RC delay.

    摘要翻译: 放电顺序控制电路包括:缓冲电路,延迟电路和用于控制内部电源的放电顺序的放电单元。 池电路存储从外部电源的电位提供的电荷。 延迟电路对存储在池电路中的电荷进行操作,并且当外部电源的电位降低到预定电位电平时,延迟产生的放电信号。 延迟电路包括具有多个级的逆变器阵列,每个级包含反相器。 多个级包括输出延迟放电信号的最后级。 只有最终级的逆变器产生RC延迟。

    VOLTAGE STEP-DOWN CIRCUIT
    5.
    发明申请
    VOLTAGE STEP-DOWN CIRCUIT 有权
    电压降压电路

    公开(公告)号:US20080231351A1

    公开(公告)日:2008-09-25

    申请号:US12051465

    申请日:2008-03-19

    IPC分类号: G05F3/02

    CPC分类号: G11C5/147

    摘要: According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.

    摘要翻译: 根据本发明的一个方面,提供了一种电压降压电路,包括:第一NMOS,其连接在通过在激活状态期间导通的PMOS的外部和内部电源电压之间,并且在待机状态期间断开 ; 连接在外部和内部电源电压之间的第二NMOS; 以及电流控制电路,其在将动作状态从活动状态切换到待机状态之后,将电流从内部电源电压吸收到地电平一段时间。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号:US5717625A

    公开(公告)日:1998-02-10

    申请号:US784963

    申请日:1997-01-16

    IPC分类号: G11C8/08 G11C11/404 G11C15/00

    CPC分类号: G11C8/08 G11C11/4045

    摘要: In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

    摘要翻译: 在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中,并且每个存储单元单元连接到位线,该半导体存储器件包括用于直接读取数据的数据的控制电路 当前一行地址指定与当前行地址相同的存储单元时,读取操作期间的寄存器单元,以及数据改变控制电路,用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据 存储单元单元中的位线接触,以及用于选择存储单元单元的存储器的相应行地址的行解码器,比存储单元单元中选择存储单元的行地址的部分高。

    Power supply circuit that outputs a voltage stepped down from a power supply voltage
    9.
    发明授权
    Power supply circuit that outputs a voltage stepped down from a power supply voltage 失效
    输出从电源电压降压的电源的电源电路

    公开(公告)号:US08134349B2

    公开(公告)日:2012-03-13

    申请号:US12404438

    申请日:2009-03-16

    IPC分类号: G05F1/613

    CPC分类号: G05F1/56

    摘要: A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.

    摘要翻译: 电源电路具有恒压电路,第一MOS晶体管,第二MOS晶体管,第三MOS晶体管,第一分压电路,输出通过将输出端子的电压除以第一分压而得到的第一分压 以及馈送有参考电压的第一差分放大器电路和第一分压,并且具有连接到第二MOS晶体管的栅极的输出。 当第一分压高于参考电压时,第一差分放大器电路输出信号以接通第二MOS晶体管,并且当第一分压电压较低时,第一差分放大器电路输出关闭第二MOS晶体管的信号 比参考电压。

    Ferroelectric random access memory device
    10.
    发明授权
    Ferroelectric random access memory device 失效
    铁电随机存取存储器件

    公开(公告)号:US07269049B2

    公开(公告)日:2007-09-11

    申请号:US11046878

    申请日:2005-02-01

    IPC分类号: G11C11/22

    CPC分类号: G11C11/22 G11C7/14

    摘要: A plurality of ferroelectric memory cells is arrayed. One terminal of each memory cells arrayed in the same column is connected in common to a first bit line. A gate of a transistor of memory cells arrayed in the same row is connected in common to a word line. The other terminal of each of memory cells arrayed in the same column or the same row is connected in common to a cell plate line. A second bit line is connected with a reference voltage supply circuit. The first and second bit lines are connected with a data read circuit. The data read circuit includes a sense amplifier and a current mirror circuit having a pair of current input node connected to the first and second bit lines, and carrying the same current flowing through one of the first and second bit line to the other bit line.

    摘要翻译: 排列多个铁电存储单元。 排列在同一列中的每个存储单元的一个端子共同连接到第一位线。 排列在同一行中的存储单元的晶体管的栅极共同连接到字线。 排列在同一列或同一行中的每个存储单元的另一个端子共同连接到单元格板线。 第二位线与参考电压供应电路连接。 第一和第二位线与数据读取电路连接。 数据读取电路包括读出放大器和电流镜像电路,其具有连接到第一和第二位线的一对电流输入节点,并且将流过第一和第二位线之一的相同电流传送到另一位线。