公开(公告)号：US5418750A

公开(公告)日：1995-05-23

申请号：US200107

申请日：1994-02-22

申请人： Shinichiro Shiratake ,  Takehiro Hasegawa ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Ryo Fukuda

发明人： Shinichiro Shiratake ,  Takehiro Hasegawa ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Ryo Fukuda

IPC分类号： G11C11/407 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C11/4097

摘要： A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups are regularly arranged in an opposite direction.

摘要翻译： 半导体存储器件包括一系列存储器单元，分别连接到存储器单元的一系列位线，一系列读出放大器，连接到包括一系列位线的预定数量位线的相应位线组，用于读取 连接到位线组的位线的存储器单元的输出数据，位线组包括至少相邻的第一和第二位线组，分配在位线和读出放大器之间并具有门的至少第一和第二晶体管，用于 选择性地连接位线和读出放大器，以及一系列控制信号线，共同连接到连接到第一位线组的第一晶体管和连接到第二位线组的第二晶体管，使得连接到第一位线组的第一晶体管 第一位线组在一个方向上规则地排列，第二晶体管连接到第二位线组 第一位线组以相反的方向规则地布置。

公开(公告)号：US5892724A

公开(公告)日：1999-04-06

申请号：US848152

申请日：1997-04-29

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Fujio Masuoka ,  Ryu Ogiwara ,  Shinichiro Shiratake ,  Shigeyoshi Watanabe

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Fujio Masuoka ,  Ryu Ogiwara ,  Shinichiro Shiratake ,  Shigeyoshi Watanabe

IPC分类号： G11C7/10 ,  G11C11/404 ,  G11C11/4096 ,  G11C11/4097 ,  G11C8/00

CPC分类号： G11C7/106 ,  G11C11/4045 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/1051 ,  G11C7/1078

摘要： A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.

摘要翻译： 读出放大器连接在存储单元阵列之间，重写寄存器与读出放大器相邻地布置，第一传输门设置在读出放大器和存储单元阵列之间，第二传输门提供在存储单元的位线之间 阵列和全局位线，以及用于控制传输门的栅极控制电路。 当读出数据被写入寄存器时，读出放大器的节点与位线和全局位线电分离。

公开(公告)号：US5625602A

公开(公告)日：1997-04-29

申请号：US446291

申请日：1995-05-22

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Fujio Masuoka ,  Ryu Ogiwara ,  Shinichiro Shiratake ,  Shigeyoshi Watanabe

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Fujio Masuoka ,  Ryu Ogiwara ,  Shinichiro Shiratake ,  Shigeyoshi Watanabe

IPC分类号： G11C7/10 ,  G11C11/404 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C7/106 ,  G11C11/4045 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/1051 ,  G11C7/1078

摘要： A sense amplifier is connected between memory cell arrays, a re-writing register is arranged in position adjacent to the sense amplifier, transfer gates are disposed between the sense amplifier and the memory cell arrays, transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.

摘要翻译： 读出放大器连接在存储单元阵列之间，重写寄存器布置在与读出放大器相邻的位置，传输门设置在读出放大器和存储单元阵列之间，传输门提供在存储单元的位线之间 阵列和全局位线，以及用于控制传输门的栅极控制电路。 当读出数据被写入寄存器时，读出放大器的节点与位线和全局位线电分离。

公开(公告)号：US5717625A

公开(公告)日：1998-02-10

申请号：US784963

申请日：1997-01-16

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

IPC分类号： G11C8/08 ,  G11C11/404 ,  G11C15/00

CPC分类号： G11C8/08 ,  G11C11/4045

摘要： In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

摘要翻译： 在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中，并且每个存储单元单元连接到位线，该半导体存储器件包括用于直接读取数据的数据的控制电路 当前一行地址指定与当前行地址相同的存储单元时，读取操作期间的寄存器单元，以及数据改变控制电路，用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据 存储单元单元中的位线接触，以及用于选择存储单元单元的存储器的相应行地址的行解码器，比存储单元单元中选择存储单元的行地址的部分高。

公开(公告)号：US20100247346A1

公开(公告)日：2010-09-30

申请号：US12739582

申请日：2008-10-21

申请人： Takehiro Hasegawa

发明人： Takehiro Hasegawa

IPC分类号： F04B35/04 ,  H01R13/52

CPC分类号： F04C23/008 ,  F04C2240/803

摘要： Provided is a terminal device for an electric compressor in which each inputting female terminal of a cluster holding a plurality of inputting female terminals for input into an electric motor built in a compressor in a resin housing is engaged with the inner end of each sealed terminal of a sealed terminal device. The terminal device is characterized in that a resin housing storing section for storing the resin housing is formed in a compressor housing, and in that the resin housing stored in the resin housing storing section is clamped between the compressor housing and a terminal plate of the sealed terminal device mounted on the compressor housing. The terminal device can prevent coming off of the inputting female terminal and undesired positional shifting of the resin housing, and can improve its assembling ability.

摘要翻译： 提供一种电动压缩机的终端装置，其中，保持多个输入母端子的群的每个输入母端子被输入到内置在树脂壳体中的压缩机中的电动马达与每个密封端子的内端接合 一个密封的终端设备。 端子装置的特征在于，在压缩机壳体中形成有用于储存树脂壳体的树脂容纳部分储存部分，并且存储在树脂容纳部分中的树脂壳体夹在压缩机壳体和密封的端子板之间 终端设备安装在压缩机壳体上。 终端装置可以防止输入母端子的脱落和树脂壳体的不期望的位置偏移，并且可以提高其组装能力。

公开(公告)号：US07344400B2

公开(公告)日：2008-03-18

申请号：US11229723

申请日：2005-09-20

申请人： Takehiro Hasegawa

发明人： Takehiro Hasegawa

IPC分类号： H01R13/52

CPC分类号： H01R13/521 ,  F04C29/0085 ,  F04C2240/803 ,  H01R13/5202 ,  H02K5/225

摘要： A terminal connection structure of a motor incorporated within a compressor for connecting feed terminals for a stator of a motor to the compressor includes a lid, which is attached to a compressor body portion for securing external feed terminals with a hermetic seal. The terminal connection structure is provided with a resin chamber on an inner surface of the lid, through which the external feed terminals extend, and a resin housing containing wire-side terminals, which are provided at ends of wires connected to the stator and which are connected to the external feed terminals. In the structure, superior insulation properties may be obtained even if the compressor size is reduced, and the productivity and assembling performance of the compressor may be improved.

摘要翻译： 并入用于将电动机的定子的供给端子连接到压缩机的电动机的端子连接结构包括：盖，其附接到压缩机主体部分，用于固定具有气密密封的外部进给端子。 端子连接结构在盖的内表面上设置有树脂室，外部馈电端子延伸穿过该树脂室，并且包括线侧端子的树脂壳体设置在连接到定子的导线的端部， 连接到外部馈电端子。 在该结构中，即使压缩机尺寸减小也可以获得优异的绝缘性能，并且可以提高压缩机的生产率和组装性能。

公开(公告)号：US07332766B2

公开(公告)日：2008-02-19

申请号：US11083156

申请日：2005-03-18

申请人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

发明人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11524 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

摘要翻译： 半导体集成电路器件包括第一和第二非易失性半导体存储器。 第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。 第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。 第二存储器具有第三选择晶体管和第二存储单元晶体管。 第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。 第一和第二栅极绝缘膜具有相同的膜厚度。 第一和第二浮栅具有相同的膜厚度。 第一和第二栅极间绝缘膜具有相同的膜厚度。 第一和第二控制栅具有相同的膜厚度。

公开(公告)号：US06994530B2

公开(公告)日：2006-02-07

申请号：US10415030

申请日：2001-10-23

申请人： Yoshiaki Fujisawa ,  Takehiro Hasegawa

发明人： Yoshiaki Fujisawa ,  Takehiro Hasegawa

IPC分类号： F04B35/04

CPC分类号： H02K33/18 ,  F04B35/045 ,  H02K1/34

摘要： A vibration type compressor related to the present invention, in which a compressor main body 3 is built into a gastight vessel 2 including a yoke 7-1, a magnetic path member 7 formed from a column-shaped core pole 7-2, a permanent magnet 12 arranged in the magnetic path, an electromagnetic coil 14 which is arranged within an annular magnetic gap 13 between the magnetic path members 7 by being supported by a mechanical vibration system to as to be able to vibrate and is wound around a lead plate to perform the connection treatment of a terminal thereof, a piston 16 connected to the electromagnetic coil 14, and a cylinder block 8 which closes the yoke 7-1 and in the interior of which is formed the cylinder portion 17 housing the piston 16, characterized in that the permanent magnet 12 is formed from a neodymium magnet or a rare-earth magnet and in that the cylindrical permanent magnet 12 is divided into four parts in the axial direction thereof, the four-part divided magnet being bonded and fixed to the side of the core pole 7-2, whereby the vibration type compressor is miniaturized and its efficiency is increased.

摘要翻译： 本发明的振动型压缩机，其特征在于，压缩机主体3内置有包括轭架7的气密容器2，由柱状芯棒7-2形成的磁路部件7，永磁体 布置在磁路中的磁体12，电磁线圈14，其布置在磁路构件7之间的环形磁隙13内，由机械振动系统支撑，以便能够振动并卷绕在引线板上 执行其端子的连接处理，连接到电磁线圈14的活塞16以及闭合轭7-1并且其内部形成有容纳活塞16的气缸部17的气缸体8，其特征在于， 永磁体12由钕磁体或稀土类磁体形成，圆柱形永久磁铁12的轴向分为四部分，四部分分磁铁为 粘结并固定在芯柱7-2的侧面，由此使振动式压缩机小型化，效率提高。

公开(公告)号：US20050218460A1

公开(公告)日：2005-10-06

申请号：US11083156

申请日：2005-03-18

申请人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

发明人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

IPC分类号： G11C16/04 ,  G11C16/02 ,  H01L21/00 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11524 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

摘要翻译： 半导体集成电路器件包括第一和第二非易失性半导体存储器。 第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。 第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。 第二存储器具有第三选择晶体管和第二存储单元晶体管。 第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。 第一和第二栅极绝缘膜具有相同的膜厚度。 第一和第二浮栅具有相同的膜厚度。 第一和第二栅极间绝缘膜具有相同的膜厚度。 第一和第二控制栅具有相同的膜厚度。

公开(公告)号：US6088290A

公开(公告)日：2000-07-11

申请号：US132644

申请日：1998-08-11

申请人： Hiroyuki Ohtake ,  Shigeo Ohshima ,  Takehiro Hasegawa

发明人： Hiroyuki Ohtake ,  Shigeo Ohshima ,  Takehiro Hasegawa

IPC分类号： G11C11/413 ,  G11C7/20 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/20

摘要： When a clock enable signal asynchronous with a clock signal is set at a high level, a power-down control circuit sets a power-down signal at a high level to release a power-down mode. When the power-down mode is released, a clock control circuit outputs an internal clock signal such that an output signal of a command decoder can be latched. According to such a constitution, a period of time from the latching of the command after releasing the power-down mode to the time when the command can be transferred will be reduced, and a high-speed operation can be attained.

摘要翻译： 当与时钟信号异步的时钟使能信号被设置为高电平时，掉电控制电路将掉电信号设置在高电平以释放掉电模式。 当释放掉电模式时，时钟控制电路输出内部时钟信号，使得可以锁存命令解码器的输出信号。 根据这样的结构，可以减少在释放掉电模式之后的命令的锁存到命令可以传送的时间段，并且可以实现高速操作。