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36 条记录 (耗时 0.026 秒)

    Data transmission apparatus with loopback topology
    1.
    发明授权
    Data transmission apparatus with loopback topology 失效
    具有环回拓扑的数据传输设备

    公开(公告)号：US4992973A

    公开(公告)日：1991-02-12

    申请号：US217002

    申请日：1988-07-08

    申请人： Toshiyuki Tamura ,  Shinji Komori ,  Hidehiro Takata ,  Tetsuo Yamasaki ,  Hiroaki Terada ,  Katsuhiko Asada

    发明人： Toshiyuki Tamura ,  Shinji Komori ,  Hidehiro Takata ,  Tetsuo Yamasaki ,  Hiroaki Terada ,  Katsuhiko Asada

    IPC分类号： G06F5/08 ,  G06F13/38 ,  H04L1/24

    CPC分类号： H04L1/24

    摘要： A data transmission apparatus which is connected with a shift register of a plural stages forming a forward path of data transmission line, and a shift register of a plural stages forming a backward path of the same, and a loop-back part therebetween, and comprises bypasses between the shift register on the forward path and on the backward path to bypass the transmitted data when significant data does not exist on the loop-back part side from a stage on which the bypass is comprised and no data stays at a stage where the bypass is comprised, so that data is transmitted at high speed, and which is constructed to be able to control the bypass from external, so that testing of circuitry is easy.

    摘要翻译： 一种数据传输装置，其与形成数据传输线的前向路径的多级的移位寄存器和形成其后向路径的多级的移位寄存器及其间的环回部分连接，并且包括 在来自包括旁路的级的环回部分侧上不存在有效数据时，在前向路径上的移位寄存器和反向路径之间绕过旁路传输数据，并且没有数据停留在 旁路被包括，使得数据以高速传输，并且被构造成能够从外部控制旁路，使得电路测试容易。

    Reduced power pipelined static data transfer apparatus
    3.
    发明授权
    Reduced power pipelined static data transfer apparatus 失效
    降低功率流水线静态数据传输设备

    公开(公告)号：US4980851A

    公开(公告)日：1990-12-25

    申请号：US284963

    申请日：1988-12-15

    申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Tetsuo Yamasaki ,  Kenji Shima

    发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Tetsuo Yamasaki ,  Kenji Shima

    IPC分类号： G06F13/38 ,  G06F5/08 ,  G06F13/42 ,  G11C7/00

    CPC分类号： G06F13/4213 ,  Y02B60/1228 ,  Y02B60/1235

    摘要： A pipelined processor is provided with a plurality of control stages controlling a datapath made up of a plurality of parallel static-type data latches. The latches each include a feedback circuit, typically a field-effect transistor, which is enabled by a data latch control signal from a particular control stage. Enabling the feedback stage consumes power. A data stagnation detection circuit detects a data stagnation in the datapath, by use of handshake control signals exchanged between the control stages. The data stagnation detection circuit inhibits enablement of the feedback circuit when no data stagnation is detected, reducing power used in the latch.

    摘要翻译： 流水线处理器设置有多个控制级，控制由多个并行静态数据锁存器组成的数据路径。 锁存器各自包括反馈电路，通常是场效应晶体管，其通过来自特定控制级的数据锁存器控制信号使能。 启用反馈级消耗电力。 数据停滞检测电路通过使用在控制级之间交换的握手控制信号来检测数据通路中的数据停滞。 当没有检测到数据停滞时，数据停滞检测电路禁止反馈电路的使能，减少锁存器中使用的功率。

    Data flow machine
    4.
    发明授权
    Data flow machine 失效
    数据流机

    公开(公告)号：US4972315A

    公开(公告)日：1990-11-20

    申请号：US166524

    申请日：1988-03-10

    申请人： Tetsuo Yamasaki ,  Kenji Shima ,  Mitsuo Meichi ,  Shinji Komori ,  Hidehiro Takata

    发明人： Tetsuo Yamasaki ,  Kenji Shima ,  Mitsuo Meichi ,  Shinji Komori ,  Hidehiro Takata

    IPC分类号： G06F9/44

    CPC分类号： G06F9/4436

    摘要： In a data flow machine, a program stored in advance is read out based on a tag included in a packet when the packet including first data is inputted from an external portion. Then, an instruction packet is formed by the content read out as a new tag and the first data, so that the instruction packet is outputted. Second data including the same tag as that included in the first data of the instruction packet read out from the program memory is detected. Firing processing is performed with respect to the first data and the second data as a pair and arithmetic processing is performed according to the instruction as a part of the tag included in an arithmetic packet, so that the arithmetic packet is outputted as a packet. The tag included in the packet is determined and the packet is outputted to an external portion or is inputted again to the internal portion.

    摘要翻译： 在数据流机器中，当从外部输入包括第一数据的分组时，基于包中包含的标签，预先存储的程序被读出。 然后，通过作为新标签读出的内容和第一数据形成指令包，从而输出指令包。 检测包括与从程序存储器读出的指令包的第一数据中包含的标签相同的标签的第二数据。 根据第一数据和第二数据作为一对进行烧制处理，并且根据作为包括在算术分组中的标签的一部分的指令进行算术处理，从而将算术分组输出为分组。 确定分组中包含的标签，并将分组输出到外部部分或再次输入到内部部分。

    Data-driven processor having an internal tag-generating system for generating a distinct tagged information and assembling with un-tagged information of an input/output data packet
    5.
    发明授权
    Data-driven processor having an internal tag-generating system for generating a distinct tagged information and assembling with un-tagged information of an input/output data packet 失效
    数据驱动处理器具有内部标签生成系统，用于生成不同的标记信息并且与输入/输出数据包的未标记信息进行组合

    公开(公告)号：US5117489A

    公开(公告)日：1992-05-26

    申请号：US471684

    申请日：1990-01-26

    申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    IPC分类号： G06F9/44

    CPC分类号： G06F9/4436

    摘要： A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved and the data output is executed in a predetermined order.

    摘要翻译： 数据驱动处理器具有分组组合单元，用于当输入数据不具有诸如目的地址等的标签信息时，将标签信息添加到顺序输入的数据，从而使得能够在不使用外部电路的情况下输入数据 ，诸如主处理器，并且提高数据输入速率，并且还具有分组输出和重排单元，用于以预定顺序重新排列输出分组流，从而仅输出数据信息，使得数据可能是 在没有任何外部电路的情况下输出，例如主机处理器，输出速率得到改善，并且以预定顺序执行数据输出。

    Retrieving data using hash memory address generated by reversing /xor bits of selected bit strings of an input packet id
    6.
    发明授权
    Retrieving data using hash memory address generated by reversing /xor bits of selected bit strings of an input packet id 失效
    使用通过输入数据包ID的所选位串的倒置/位数产生的散列存储器地址来检索数据

    公开(公告)号：US5182799A

    公开(公告)日：1993-01-26

    申请号：US416887

    申请日：1989-10-04

    申请人： Toshiyuki Tamura ,  Masaki Fujita ,  Shinji Komori ,  Hisakazu Sato ,  Hidehiro Takata

    发明人： Toshiyuki Tamura ,  Masaki Fujita ,  Shinji Komori ,  Hisakazu Sato ,  Hidehiro Takata

    IPC分类号： G06F15/82 ,  G06F9/44 ,  G06F17/30

    CPC分类号： G06F17/30949 ,  G06F9/4436

    摘要： A data retrieving apparatus having an address generator for selecting partly at least one of bit strings of the identification data and generating a hashed address by a reversible operation thereof when a packet having an operand data and a plurality of identification data is inputted, a hash memory for being accessed by the hashed address, a match detector for comparing the identification data of the stored packet with the identification data of the inputted packet and judging match/mismatch thereof when a valid packet is already stored in the hashed address generated from the inputted packet, an associative memory unit for storing the identification data of the inputted packet as a retrieval data when the match detector judges to be mismatch, and judging match/mismatch of the identification data already stored with the identification data of the inputted packet when a packet is inputted, and an output selector for selecting an output from the hash memory or the associative memory unit in response to the result of judgement of said associative memory unit.

    摘要翻译： 一种数据检索装置，具有地址发生器，用于当输入具有操作数据和多个识别数据的分组时，部分地选择识别数据的比特串中的一个以及通过其可逆操作产生散列的地址，哈希存储器 用于通过散列地址访问的匹配检测器，用于将存储的分组的识别数据与输入的分组的识别数据进行比较，并且当有效分组已经存储在从输入分组生成的散列地址中时，判断匹配/不匹配 相关联存储单元，用于当匹配检测器判断为不匹配时，将输入的分组的识别数据存储为检索数据，并且当分组是分组时，判断已经存储的识别数据与输入分组的识别数据的匹配/不匹配 以及用于选择来自散列存储器或关联存储器uni的输出的输出选择器 响应于所述关联存储器单元的判断结果。

    Data-driven processor having an output unit for providing only operand data in a predetermined order
    8.
    发明授权
    Data-driven processor having an output unit for providing only operand data in a predetermined order 失效
    数据驱动处理器具有用于仅以预定顺序提供操作数数据的输出单元

    公开(公告)号：US5392442A

    公开(公告)日：1995-02-21

    申请号：US837128

    申请日：1992-02-19

    申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    IPC分类号： E04B1/41 ,  F16B13/08 ,  F16B13/14 ,  G06F9/06

    CPC分类号： F16B13/0808 ,  Y10S411/908

    摘要： A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved, and the data output is executed in a predetermined order.

    摘要翻译： 数据驱动处理器具有分组组合单元，用于当输入数据不具有诸如目的地址等的标签信息时，将标签信息添加到顺序输入的数据，从而使得能够在不使用外部电路的情况下输入数据 ，诸如主处理器，并且提高数据输入速率，并且还具有分组输出和重排单元，用于以预定顺序重新排列输出分组流，从而仅输出数据信息，使得数据可能是 在没有任何外部电路的情况下输出，诸如主处理器，输出速率得到改善，并且以预定顺序执行数据输出。

    Hand-shake type data transfer control circuit
    9.
    发明授权
    Hand-shake type data transfer control circuit 失效
    手抖式数据传输控制电路

    公开(公告)号：US4882704A

    公开(公告)日：1989-11-21

    申请号：US157194

    申请日：1988-02-17

    申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai

    发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai

    IPC分类号： G06F13/42 ,  H04J3/04

    CPC分类号： G06F7/00 ,  G06F13/4213 ,  H04J3/047 ,  G06F2207/3864

    摘要： A hand-shake type control circuit for controlling a data transfer circuit according to the status of a data transfer request signal. The data transfer request signal is initially received at a NAND gate and is also directly coupled to the reset input of are set flip-flop. The output of the NAND gate is used as a first control signal to set the flip-flop and to cause another circuit to activate data transfer. The flip-flop output is a second control signal which is reset only when the transfer request signal changes from an active to an inactive status. The second control signal is coupled to an input of the NAND gate and inactivates the first control signal. Thus, data transfer cannot recur until after the data transfer request signal changes to an inactive status so that parasitic oscillations are eliminated. The flip-flop consists of two, two input NAND gates that are located out of the path of data transfer and that are easier to fabricate than the prior art D flip-flop.

    摘要翻译： 一种用于根据数据传送请求信号的状态控制数据传送电路的握手型控制电路。 数据传送请求信号最初在NAND门处被接收并且也直接耦合到被设置的触发器的复位输入。 NAND门的输出用作第一控制信号以设置触发器并使另一电路激活数据传输。 触发器输出是仅在传送请求信号从活动状态变为非活动状态时才复位的第二控制信号。 第二控制信号耦合到NAND门的输入并使第一控制信号无效。 因此，在数据传输请求信号变为无效状态之后，数据传送不能重复，以便消除寄生振荡。 触发器由两个，两个输入NAND门组成，它们位于数据传输路径之外，并且比现有技术的D触发器更容易制造。