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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
    半导体集成电路设备

    公开(公告)号：US20090129173A1

    公开(公告)日：2009-05-21

    申请号：US12269098

    申请日：2008-11-12

    申请人： Shinya KAJIYAMA ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Shinya KAJIYAMA ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C7/00 ,  G11C8/08 ,  G11C8/00 ,  G11C7/06

    CPC分类号： G11C7/1039 ,  G11C7/1075 ,  G11C16/26

    摘要： The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

    摘要翻译： 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行流水线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。

    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07848177B2

    公开(公告)日：2010-12-07

    申请号：US12269098

    申请日：2008-11-12

    申请人： Shinya Kajiyama ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Shinya Kajiyama ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1039 ,  G11C7/1075 ,  G11C16/26

    摘要： The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

    摘要翻译： 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行管线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。

    Information processor
    3.
    发明申请
    Information processor 有权
    信息处理器

    公开(公告)号：US20070226405A1

    公开(公告)日：2007-09-27

    申请号：US11703762

    申请日：2007-02-08

    申请人： Takao Watanabe ,  Motokazu Ozawa ,  Tomonori Sekiguchi

    发明人： Takao Watanabe ,  Motokazu Ozawa ,  Tomonori Sekiguchi

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0802 ,  G06F2212/2515 ,  G11C29/76 ,  Y02D10/13

    摘要： In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

    摘要翻译： 在包括诸如DRAM等存储器件的信息处理器中，通过降低存储器件的功耗并有效地修复缺陷位，实现了高度可靠的信息处理器。 在包括诸如DRAM的外部存储器的信息处理器中，设置存取时间小于外部存储器的功耗的第二存储器，并且将外部存储器和修复数据的高速缓存数据存储在该第二存储器中 。 对于通过主缓存控制器从中央处理单元给出的输入地址，存储器控制器参考用于高速缓存的标签存储器和用于修复的标签存储器以及当缓存的标签存储器中的一个或两个时，确定命中或未命中 并且用于修复的标签存储器被命中，它访问第二存储器。

    Information storage device and storage media
    4.
    发明授权
    Information storage device and storage media 有权
    信息存储设备和存储介质

    公开(公告)号：US08134905B2

    公开(公告)日：2012-03-13

    申请号：US12261032

    申请日：2008-10-30

    申请人： Takao Watanabe ,  Toshimichi Shintani ,  Takeshi Maeda ,  Akemi Hirotsune ,  Tomonori Sekiguchi

    发明人： Takao Watanabe ,  Toshimichi Shintani ,  Takeshi Maeda ,  Akemi Hirotsune ,  Tomonori Sekiguchi

    IPC分类号： G11B7/00

    CPC分类号： G11B7/0025 ,  G11B7/24006

    摘要： In an information memory apparatus having minute areas for storing information arranged in x, y and z directions three-dimensionally, parallel rays are irradiated to a memory area MA in a direction perpendicular to a z-axis to take projection images of the memory area MA while rotating the memory area MA around the z-axis little by little. The light rays irradiated at this time have a size which covers at least a direction of an x-y plane of the memory area. A computation unit PU finds data and addresses of minute areas distributed three-dimensionally by performing computation based upon the principle of computer tomography on the projection images. As for data writing, a change is given to optical transmissivity or light emission characteristics by irradiating laser light focused by a lens OL placed outside the memory area to a desired minute area and causing heat denaturation within the pertinent minute area.

    摘要翻译： 在具有用于以三维方式存储以x，y和z方向排列的信息的微小区域的信息存储装置中，在垂直于z轴的方向上将平行光线照射到存储区域MA，以拍摄存储区域MA的投影图像 同时围绕z轴逐渐旋转存储区域MA。 此时照射的光线具有至少覆盖存储区域的x-y平面的方向的尺寸。 计算单元PU通过基于投影图像上的计算机断层摄影的原理执行计算，找到三维分布的微小区域的数据和地址。 对于数据写入，通过将放置在存储区域外部的透镜OL聚焦的激光照射到期望的微小区域并且在相关的微小区域内引起热变性，来对光学透射率或发光特性进行改变。

    Information processor with memory defect repair
    5.
    发明授权
    Information processor with memory defect repair 有权
    信息处理器内存缺陷修复

    公开(公告)号：US07809920B2

    公开(公告)日：2010-10-05

    申请号：US11703762

    申请日：2007-02-08

    申请人： Takao Watanabe ,  Motokazu Ozawa ,  Tomonori Sekiguchi

    发明人： Takao Watanabe ,  Motokazu Ozawa ,  Tomonori Sekiguchi

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0802 ,  G06F2212/2515 ,  G11C29/76 ,  Y02D10/13

    摘要： In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

    摘要翻译： 在包括诸如DRAM等存储器件的信息处理器中，通过降低存储器件的功耗并有效地修复缺陷位，实现了高度可靠的信息处理器。 在包括诸如DRAM的外部存储器的信息处理器中，设置存取时间小于外部存储器的功耗的第二存储器，并且将外部存储器和修复数据的高速缓存数据存储在该第二存储器中 。 对于通过主缓存控制器从中央处理单元给出的输入地址，存储器控制器参考用于高速缓存的标签存储器和用于修复的标签存储器以及当缓存的标签存储器中的一个或两个时，确定命中或未命中 并且用于修复的标签存储器被命中，它访问第二存储器。