公开(公告)号：US5721601A

公开(公告)日：1998-02-24

申请号：US532484

申请日：1995-09-22

申请人： Toshifumi Yamaji ,  Kou Masahara ,  Nobuhiko Oda ,  Koji Suzuki ,  Shiro Nakanishi ,  Hisashi Abe ,  Kiyoshi Yoneda ,  Yoshihiro Morimoto

发明人： Toshifumi Yamaji ,  Kou Masahara ,  Nobuhiko Oda ,  Koji Suzuki ,  Shiro Nakanishi ,  Hisashi Abe ,  Kiyoshi Yoneda ,  Yoshihiro Morimoto

IPC分类号： G02F1/1343 ,  G02F1/1333 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/786

CPC分类号： G02F1/136227 ,  G02F2001/133357

摘要： A liquid crystal display unit is described, which includes a first substrate, a second substrate opposing to the first substrate, pixel driving elements, first and second insulation layers, a planarizing film and a liquid crystal layer. The pixel driving elements are disposed on the first substrate and between the first and second substrates. The first insulation layer is deposited over the first substrate and the pixel driving elements. The planarizing film is formed on the first insulation layer. This planarizing film provides a substantially flat surface over the first substrate to minimize a height of a step present between an area corresponding to each pixel driving element and an area locating adjacent to the pixel driving element on the first substrate. The second insulation layer is formed on the planarizing film. The display electrodes are formed on the second insulation layer and electrically connected to the pixel driving elements, respectively. The liquid crystal layer is located between the first substrate and said second substrate.

摘要翻译： 描述了一种液晶显示单元，其包括第一基板，与第一基板相对的第二基板，像素驱动元件，第一和第二绝缘层，平坦化膜和液晶层。 像素驱动元件设置在第一基板上并且在第一和第二基板之间。 第一绝缘层沉积在第一衬底和像素驱动元件上。 平坦化膜形成在第一绝缘层上。 该平坦化膜在第一基板上提供基本上平坦的表面，以使在与每个像素驱动元件相对应的区域和与第一基板上的像素驱动元件相邻定位的区域之间存在的台阶的高度最小化。 第二绝缘层形成在平坦化膜上。 显示电极分别形成在第二绝缘层上并与像素驱动元件电连接。 液晶层位于第一基板和第二基板之间。

公开(公告)号：US06867075B2

公开(公告)日：2005-03-15

申请号：US10378359

申请日：2003-03-03

申请人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

发明人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

IPC分类号： H01L27/08 ,  H01L21/318 ,  H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å) where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

摘要翻译： 在配置有栅电极的透明基板上，淀积作为栅绝缘膜的氮化硅膜和氧化硅膜，形成作为有源区的半导体膜的多晶硅膜。 在对应于栅电极的多晶硅膜上，设置有阻挡层，并且沉积作为层间绝缘膜的氧化硅膜和氮化硅膜以覆盖该阻挡层。 挡块的膜厚度T0设定在800〜1200埃的范围内。 此外，阻挡层的膜厚度T0设定在满足以下表达式的范围内：其中，T1是氧化硅膜的膜厚度，T2是氮化硅膜的膜厚度。

公开(公告)号：US06815272B2

公开(公告)日：2004-11-09

申请号：US10008389

申请日：2001-11-06

申请人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

发明人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

IPC分类号： H01L2100

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78678

摘要： In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper is removed. The ion stopper does not remain in the interlayer insulating film lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper, and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer. The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

摘要翻译： 在底栅型薄膜晶体管制造方法中，在离子掺杂之后，去除离子塞。 离子限制器不会残留在位于栅电极正上方的层间绝缘膜中。 薄膜晶体管具有这样的结构：离子阻挡层和层间绝缘层至少与半导体层的沟道区域直接接触。 层间绝缘膜和半导体层4之间的界面附近的杂质浓度为10 18原子/ cc以下。 这种结构可以防止反向通道现象，并减少由制造变化引起的特性变化。

公开(公告)号：US06191452B1

公开(公告)日：2001-02-20

申请号：US09162836

申请日：1998-09-29

申请人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

发明人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

IPC分类号： H01L2900

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

摘要翻译： 在配置有栅电极的透明基板上，淀积作为栅绝缘膜的氮化硅膜和氧化硅膜，形成作为有源区的半导体膜的多晶硅膜。 在对应于栅电极的多晶硅膜上，设置有阻挡层，并且沉积作为层间绝缘膜的氧化硅膜和氮化硅膜以覆盖该阻挡层。 挡块的膜厚度T0设定在800〜1200埃的范围内。 此外，阻挡层的膜厚度T0设定在满足以下表达式的范围内：其中，T1是氧化硅膜的膜厚度，T2是氮化硅膜的膜厚度。

公开(公告)号：US06555419B2

公开(公告)日：2003-04-29

申请号：US09746253

申请日：2000-12-21

申请人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

发明人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

IPC分类号： H01L2100

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

摘要翻译： 在配置有栅电极的透明基板上，淀积作为栅绝缘膜的氮化硅膜和氧化硅膜，形成作为有源区的半导体膜的多晶硅膜。 在对应于栅电极的多晶硅膜上，设置有阻挡层，并且沉积作为层间绝缘膜的氧化硅膜和氮化硅膜以覆盖该阻挡层。 挡块的膜厚度T0设定在800〜1200埃的范围内。 此外，阻挡层的膜厚度T0设定在满足以下表达式的范围内：其中，T1是氧化硅膜的膜厚度，T2是氮化硅膜的膜厚度。

公开(公告)号：US06265247B1

公开(公告)日：2001-07-24

申请号：US09334444

申请日：1999-06-15

申请人： Shiro Nakanishi ,  Nobuhiko Oda

发明人： Shiro Nakanishi ,  Nobuhiko Oda

IPC分类号： H01L2100

CPC分类号： H01L29/66765 ,  H01L21/76804 ,  H01L29/41733 ,  Y10S438/978

摘要： On a transparent substrate, on which is positioned a gate electrode, a silicon nitride film and a silicon oxide film are formed as gate insulating films, and furthermore a polycrystalline silicon film is formed as a semiconductor film to become an active region. A stopper is positioned on the polycrystalline silicon film to correspond to a gate electrode, and a silicon oxide film, a silicon nitride film, and a silicon oxide film are formed as interlayer insulating film so as to cover the stopper. Contact holes are formed in the layer insulating film to correspond to a source region and a drain region, and a source electrode and a drain electrode are positioned through these contact holes. Since the silicon oxide film having a fast etching rate is formed on the silicon nitride film having a slow etching rate, the etching from the silicon oxide film above the silicon nitride film dominates when forming the contact holes in the layer insulating film so that the etched shape of the silicon nitride film assumes a tapered shape widening toward the top.

摘要翻译： 在其上设置有栅电极的透明基板上形成氮化硅膜和氧化硅膜作为栅极绝缘膜，此外，形成多晶硅膜作为半导体膜以成为有源区。 阻挡器位于多晶硅膜上以对应于栅电极，并且形成氧化硅膜，氮化硅膜和氧化硅膜作为层间绝缘膜以覆盖止动器。 在层间绝缘膜上形成有与源极区域和漏极区域对应的接触孔，源极电极和漏极电极通过这些接触孔定位。 由于在具有缓慢蚀刻速率的氮化硅膜上形成具有快蚀刻速率的氧化硅膜，所以在形成层间绝缘膜中的接触孔时，来自氮化硅膜上方的氧化硅膜的蚀刻占主导地位，使得蚀刻 氮化硅膜的形状呈朝向顶部变宽的锥形形状。

公开(公告)号：US20050042809A1

公开(公告)日：2005-02-24

申请号：US10946037

申请日：2004-09-21

申请人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

发明人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

IPC分类号： G02F1/136 ,  G02F1/00 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78678

摘要： In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

公开(公告)号：US20050035348A1

公开(公告)日：2005-02-17

申请号：US10945233

申请日：2004-09-20

申请人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

发明人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

IPC分类号： G02F1/136 ,  G02F1/00 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78678

摘要： In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

摘要翻译： 在底栅型薄膜晶体管制造方法中，在离子掺杂之后，去除离子塞（55）。 离子限制器（55）不会留在位于栅电极正上方的层间绝缘膜（8）中。 薄膜晶体管具有这样的结构：离子阻挡层（55）和层间绝缘层至少与半导体层（4）的沟道区域直接接触。 层间绝缘膜和半导体层4之间的界面附近的杂质浓度为10 18原子/ cc以下。 这种结构可以防止反向通道现象，并减少由制造变化引起的特性变化。

公开(公告)号：US07163850B2

公开(公告)日：2007-01-16

申请号：US10945233

申请日：2004-09-20

申请人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

发明人： Nobuhiko Oda ,  Toshifumi Yamaji ,  Shiro Nakanishi ,  Yoshihiro Morimoto ,  Kiyoshi Yoneda

IPC分类号： H01L21/00

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78678

摘要： In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

摘要翻译： 在底栅型薄膜晶体管制造方法中，在离子掺杂之后，去除离子塞（55）。 离子限制器（55）不会留在位于栅电极正上方的层间绝缘膜（8）中。 薄膜晶体管具有这样的结构：离子阻挡层（55）和层间绝缘层至少与半导体层（4）的沟道区域直接接触。 层间绝缘膜与半导体层4之间的界面附近的杂质浓度为10原子/ cc以下。 这种结构可以防止反向通道现象，并减少由制造变化引起的特性变化。

公开(公告)号：US5962916A

公开(公告)日：1999-10-05

申请号：US162209

申请日：1998-09-28

申请人： Shiro Nakanishi ,  Nobuhiko Oda

发明人： Shiro Nakanishi ,  Nobuhiko Oda

IPC分类号： H01L21/318 ,  H01L21/336 ,  H01L21/768 ,  H01L29/417 ,  H01L29/786 ,  H01L23/58 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L29/66765 ,  H01L21/76804 ,  H01L29/41733 ,  Y10S438/978

摘要： On a transparent substrate, on which is positioned a gate electrode, a silicon nitride film and a silicon oxide film are formed as gate insulating films, and furthermore a polycrystalline silicon film is formed as a semiconductor film to become an active region. A stopper is positioned on the polycrystalline silicon film to correspond to a gate electrode, and a silicon oxide film, a silicon nitride film, and a silicon oxide film are formed as interlayer insulating film so as to cover the stopper. Contact holes are formed in the layer insulating film to correspond to a source region and a drain region, and a source electrode and a drain electrode are positioned through these contact holes. Since the silicon oxide film having a fast etching rate is formed on the silicon nitride film having a slow etching rate, the etching from the silicon oxide film above the silicon nitride film dominates when forming the contact holes in the layer insulating film so that the etched shape of the silicon nitride film assumes a tapered shape widening toward the top.

摘要翻译： 在其上设置有栅电极的透明基板上形成氮化硅膜和氧化硅膜作为栅极绝缘膜，此外，形成多晶硅膜作为半导体膜以成为有源区。 阻挡器位于多晶硅膜上以对应于栅电极，并且形成氧化硅膜，氮化硅膜和氧化硅膜作为层间绝缘膜以覆盖止动器。 在层间绝缘膜上形成有与源极区域和漏极区域对应的接触孔，源极电极和漏极电极通过这些接触孔定位。 由于在具有缓慢蚀刻速率的氮化硅膜上形成具有快蚀刻速率的氧化硅膜，所以在形成层间绝缘膜中的接触孔时，来自氮化硅膜上方的氧化硅膜的蚀刻占主导地位，使得蚀刻 氮化硅膜的形状呈朝向顶部变宽的锥形形状。