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公开(公告)号：US08587091B2
公开(公告)日：2013-11-19
申请号：US13533251
申请日：2012-06-26
申请人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
发明人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/34 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/73267 , H01L2224/82039 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/83 , H01L2924/00 , H01L2224/82
摘要： A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
摘要翻译： 一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。
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公开(公告)号：US08314482B2
公开(公告)日：2012-11-20
申请号：US11905869
申请日：2007-10-05
申请人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
发明人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
IPC分类号： H01L23/02
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/34 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/73267 , H01L2224/82039 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/83 , H01L2924/00 , H01L2224/82
摘要： This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
摘要翻译： 本发明涉及一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。
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公开(公告)号：US07294920B2
公开(公告)日：2007-11-13
申请号：US11186840
申请日：2005-07-22
申请人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
发明人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
IPC分类号： H01L23/04
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/34 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/73267 , H01L2224/82039 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/83 , H01L2924/00 , H01L2224/82
摘要： This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
摘要翻译： 本发明涉及一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。
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公开(公告)号：US20070197018A1
公开(公告)日：2007-08-23
申请号：US11785612
申请日：2007-04-19
申请人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
发明人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/34 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/73267 , H01L2224/82039 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/83 , H01L2924/00 , H01L2224/82
摘要： This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
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公开(公告)号：US20060019484A1
公开(公告)日：2006-01-26
申请号：US11186840
申请日：2005-07-22
申请人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
发明人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/34 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/73267 , H01L2224/82039 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/83 , H01L2924/00 , H01L2224/82
摘要： This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
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公开(公告)号：US20120267765A1
公开(公告)日：2012-10-25
申请号：US13533251
申请日：2012-06-26
申请人： Shou-Lung CHEN , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
发明人： Shou-Lung CHEN , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
IPC分类号： H01L23/498 , H01L23/544
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/34 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/73267 , H01L2224/82039 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/83 , H01L2924/00 , H01L2224/82
摘要： A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
摘要翻译： 一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。
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公开(公告)号：US07528009B2
公开(公告)日：2009-05-05
申请号：US11785612
申请日：2007-04-19
申请人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
发明人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/34 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/73267 , H01L2224/82039 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/83 , H01L2924/00 , H01L2224/82
摘要： This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
摘要翻译： 本发明涉及一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。
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公开(公告)号：US20080029870A1
公开(公告)日：2008-02-07
申请号：US11905869
申请日：2007-10-05
申请人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
发明人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/34 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/73267 , H01L2224/82039 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/83 , H01L2924/00 , H01L2224/82
摘要： This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
摘要翻译： 本发明涉及一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。
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