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    Virtual machine system having an extended storage
    1.
    发明授权
    Virtual machine system having an extended storage 失效
    具有扩展存储的虚拟机系统

    公开(公告)号：US5341484A

    公开(公告)日：1994-08-23

    申请号：US476434

    申请日：1990-05-24

    申请人： Shunji Tanaka ,  Akira Yamaoka ,  Hidenori Umeno ,  Masatoshi Haraguchi ,  Kiyoshi Ogawa ,  Keiji Saijo ,  Katsumi Takeda

    发明人： Shunji Tanaka ,  Akira Yamaoka ,  Hidenori Umeno ,  Masatoshi Haraguchi ,  Kiyoshi Ogawa ,  Keiji Saijo ,  Katsumi Takeda

    IPC分类号： G06F12/06 ,  G06F12/10 ,  G06F12/00

    CPC分类号： G06F12/109 ,  G06F12/0623

    摘要： A virtual machine system in which a plurality of operating systems (OS's) can run on one computer including a physical main storage (physical MS), and at least one physical extended storage (physical ES), each operating system (OS) of the OS's having a virtual MS on the physical MS and at least one virtual ES on the at least one physical ES. The system includes a first address translator for translating a virtual ES address designated by an instruction issued by one OS of the OS's on a virtual space generated by the one OS on one virtual ES of the at least one virtual ES of the one OS to a virtual physical ES address on the one virtual ES based on the virtual ES address and an address of an ES relocation table on the virtual MS of the one OS or an ES relocation register in the computer, the one virtual ES being on one physical ES of the at least one physical ES of the computer, and a second address translator for translating the virtual physical ES address to a physical ES address on the one physical ES based on the virtual physical ES address and a start address of the one virtual ES in the one physical ES.

    摘要翻译： PCT No.PCT / JP89 / 00983 Sec。 371日期1990年5月24日 102（e）日期1990年5月24日PCT提交1989年9月28日PCT公布。 公开号WO90 / 05338 日期：1990年5月17日。一种其中多个操作系统（OS）可以在包括物理主存储（物理MS）和至少一个物理扩展存储（物理ES））的计算机上运行的虚拟机系统，每个操作系统 （OS）在物理MS上具有虚拟MS并且在至少一个物理ES上具有至少一个虚拟ES。 该系统包括第一地址转换器，用于将由OS的一个OS发出的指令指定的虚拟ES地址在由该OS的至少一个虚拟ES的一个虚拟ES上由一个OS产生的虚拟空间上指定给 基于虚拟ES地址的一个虚拟ES上的虚拟物理ES地址和计算机中的一个OS的虚拟MS或ES重定位寄存器上的ES重定位表的地址，一个虚拟ES位于一个物理ES上 所述计算机的所述至少一个物理ES和第二地址转换器，用于基于所述虚拟物理ES地址和所述虚拟物理ES地址中的所述一个虚拟ES的起始地址将所述虚拟物理ES地址转换为所述一个物理ES上的物理ES地址 一个物理ES。

    Multiprocessor system statically dividing processors into groups allowing processor of selected group to send task requests only to processors of selected group
    2.
    发明授权
    Multiprocessor system statically dividing processors into groups allowing processor of selected group to send task requests only to processors of selected group 失效
    多处理器系统将处理器静态分为允许所选组的处理器仅将任务请求发送到所选组的处理器的组

    公开(公告)号：US5307495A

    公开(公告)日：1994-04-26

    申请号：US735674

    申请日：1991-07-29

    申请人： Satoshi Seino ,  Hidenori Umeno ,  Kiyoshi Ogawa ,  Katsumi Takeda

    发明人： Satoshi Seino ,  Hidenori Umeno ,  Kiyoshi Ogawa ,  Katsumi Takeda

    IPC分类号： G06F9/46 ,  C07C17/00 ,  C07C67/00 ,  G06F15/16 ,  G06F15/163 ,  G06F15/17 ,  G06F15/177 ,  G06F13/00

    CPC分类号： G06F9/52

    摘要： In a computer system capable of being configured in a multiprocessor system, a plurality of virtual machines are grouped by object of use to define a plurality of processor groups. Each processor has an identifier for a processor group to which it belongs. When an instruction which requires synchronous execution among the processors is executed, the processor identifies the processor group to which it belongs and requests the synchronous execution of the instruction to only the processors in the group. In another aspect, each processor which has a request for execution refers to its own identifier to determine if the request is from a processor of the same group in order to determine whether it should execute the instruction or not. When the processor completes the execution of the instruction, it sends an end signal to the requesting processor so that another instruction from other processors in the same group can be executed.

    摘要翻译： 在能够被配置在多处理器系统中的计算机系统中，多个虚拟机通过使用对象分组以定义多个处理器组。 每个处理器具有它所属的处理器组的标识符。 当执行需要在处理器之间进行同步执行的指令时，处理器识别它所属的处理器组，并请求仅向该组中的处理器指令的同步执行。 在另一方面，具有执行请求的每个处理器是指其自己的标识符，以确定该请求是否来自同一组的处理器，以便确定它是否应该执行该指令。 当处理器完成指令的执行时，它向发出请求的处理器发送结束信号，从而可以执行来自同一组中的其他处理器的另一指令。

    Timing generator, solid-state imaging device and camera system
    3.
    发明授权
    Timing generator, solid-state imaging device and camera system 有权
    定时发生器，固态成像装置和相机系统

    公开(公告)号：US07420606B2

    公开(公告)日：2008-09-02

    申请号：US10891868

    申请日：2004-07-14

    申请人： Katsumi Takeda ,  Junji Tokumoto ,  Yoshiaki Sone ,  Tsuyoshi Hasuka

    发明人： Katsumi Takeda ,  Junji Tokumoto ,  Yoshiaki Sone ,  Tsuyoshi Hasuka

    IPC分类号： H04N3/14 ,  H04N5/335

    CPC分类号： H04N5/335

    摘要： A timing generator, includes: a first memory circuit that stores timing generation information; a first register for holding the timing generation information in the first memory circuit; a first external input part for accessing to the first register so as to rewrite data therein; a selector that selects one of the first memory circuit and the first external input part in order to conduct writing of data in the first register; and a pulse generation part that generates a pulse timing in accordance with the timing generation information held in the first register so as to output a single or a plurality of pulses. A pulse timing required for driving a solid-state imaging device and the like can be generated easily and the timing generation can be rewritten externally.

    摘要翻译： 一种定时发生器，包括：存储定时产生信息的第一存储器电路; 用于在第一存储器电路中保持定时产生信息的第一寄存器; 第一外部输入部分，用于访问第一寄存器，以便在其中重写数据; 选择器，其选择第一存储器电路和第一外部输入部分中的一个，以便在第一寄存器中进行数据的写入; 以及脉冲生成部，其根据保持在第一寄存器中的定时生成信息生成脉冲定时，以输出单个或多个脉冲。 可以容易地生成用于驱动固态成像装置等所需的脉冲定时，并且可以从外部重写定时生成。

    Digital radiocommunication terminal
    6.
    发明授权
    Digital radiocommunication terminal 失效
    数字无线电通信终端

    公开(公告)号：US5696792A

    公开(公告)日：1997-12-09

    申请号：US356464

    申请日：1994-12-15

    申请人： Shigeyuki Sudo ,  Yasuaki Takahara ,  Katsumi Takeda ,  Jun Yamada

    发明人： Shigeyuki Sudo ,  Yasuaki Takahara ,  Katsumi Takeda ,  Jun Yamada

    IPC分类号： H03D7/16 ,  H04B1/10 ,  H04B1/40 ,  H04L27/18 ,  H04L27/10

    CPC分类号： H04L27/18 ,  H03D7/163 ,  H04B1/406

    摘要： The number of oscillators required to construct a digital radiocommunication terminal can be reduced and a circuit used for the digital radiocommunication terminal can be reduced in size. For this purpose, the digital radiocommunication terminal for effecting information transmission using an N (integer)-phase-shift-keyed signal (identification symbol number N=4 upon .pi./4 shifted QPSK modulation), is constructed such that an oscillation frequency generated from a reference oscillator employed with a frequency synthesizer is selected to have a common multiple of a second intermediate frequency and an identification symbol phase N and is supplied to a detector for outputting received data therefrom.

    摘要翻译： 可以减少构造数字无线电通信终端所需的振荡器的数量，并且可以减小用于数字无线电通信终端的电路的尺寸。 为此，使用N（整数）相移键控信号（在pi / 4移位QPSK调制时的识别码元号N = 4）进行信息传输的数字无线电通信终端被构造成使得从 与频率合成器一起使用的参考振荡器被选择为具有第二中频和识别符号相位N的公倍数，并被提供给用于从其输出接收数据的检测器。

    Data processing unit which can access more registers than the registers indicated by the register fields in an instruction
    7.
    发明授权
    Data processing unit which can access more registers than the registers indicated by the register fields in an instruction 失效
    数据处理单元可以访问比指令中的寄存器字段指示的寄存器更多的寄存器

    公开(公告)号：US5581721A

    公开(公告)日：1996-12-03

    申请号：US600155

    申请日：1996-02-12

    申请人： Hideo Wada ,  Katsumi Takeda ,  Yasuhiro Inagami ,  Hiroaki Fujii

    发明人： Hideo Wada ,  Katsumi Takeda ,  Yasuhiro Inagami ,  Hiroaki Fujii

    IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/46 ,  G06F17/16 ,  G06F12/00

    CPC分类号： G06F9/30127 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/462

    摘要： The data processing unit includes a greater number of physical floating point registers than the number of floating point registers accessible by an instruction, window start point register having a plurality of bits, 1-bit window start pointer valid register, conversion apparatus for converting a floating point register number in an instruction to a physical floating point register number when the value of the window start pointer valid register is 1, and changing the pattern of this conversion by a value obtained from the value of the window start pointer register or the value of a window stride designated in a specific instruction, and the value of the window start pointer register. Also provided is an instruction controller for detecting a window start pointer set instruction for setting a value to the window start pointer register, a floating point register pre-load instruction for converting the floating point register number in the instruction to a physical floating point register number by the conversion circuit from the value obtained from the value of the window start pointer register and the value of the window stride, and storing a main memory data in the physical floating point register indicated by the physical floating point register number.

    摘要翻译： 数据处理单元包括比指令可访问的浮点寄存器数量多的物理浮点寄存器数量，具有多个位的窗口起始点寄存器，1位窗口开始指针有效寄存器，用于转换浮点数的转换装置 当窗口开始指针有效寄存器的值为1时，在物理浮点寄存器编号的指令中指定点寄存器号，并且通过从窗口开始指针寄存器的值获得的值来改变该转换的模式， 在特定指令中指定的窗口步长，以及窗口起始指针寄存器的值。 还提供了一种用于检测用于将窗口开始指针寄存器的值设置的窗口开始指针集指令的指令控制器，用于将指令中的浮点寄存器号转换为物理浮点寄存器号的浮点寄存器预加载指令 通过转换电路根据从窗口开始指针寄存器的值和窗口步幅获得的值，并将主存储器数据存储在由物理浮点寄存器号表示的物理浮点寄存器中。

    Timing generator for solid-state imaging device
    8.
    发明授权
    Timing generator for solid-state imaging device 失效
    固态成像装置的定时发生器

    公开(公告)号：US06873366B2

    公开(公告)日：2005-03-29

    申请号：US09788504

    申请日：2001-02-21

    申请人： Shinichi Tashiro ,  Katsumi Takeda

    发明人： Shinichi Tashiro ,  Katsumi Takeda

    IPC分类号： H04N5/335 ,  H04N5/341 ,  H04N5/369 ,  H04N5/372 ,  H04N5/376 ,  G06F1/06 ,  G06F1/08 ,  H04N5/228

    CPC分类号： H04N5/335

    摘要： To reduce the amount of data that should be stored on a memory-built-in timing generator for generating timing pulses for use to drive a solid-state imaging device, V- and H-counters, three ROMs, V- and H-comparators and combinatorial logic circuit are provided. The V- and H-counters perform a count operation responsive to vertical and horizontal sync signal pulses as respective triggers. One of the ROMs stores time-series data representing a logical level repetitive pattern of an output pulse train. The other two ROMs store edge data representing at what counts of the V- and H-counters control pulses should change their logical levels. The V- and H-comparators and the combinatorial logic circuit change the logical levels of the control pulses when the counts of the V- and H-counters match the edge data. The comparators and logic circuit also output, as the timing pulses, results of logical operations performed on the output pulse train, represented by the time-series data, and the control pulses.

    摘要翻译： 为了减少存储在存储器内置定时发生器中的数据量，用于产生用于驱动固态成像装置的定时脉冲，V和H计数器，三个ROM，V和H比较器 并提供组合逻辑电路。 V和H计数器响应垂直和水平同步信号脉冲作为相应触发器执行计数操作。 其中一个ROM存储表示输出脉冲串的逻辑电平重复模式的时间序列数据。 另外两个ROM存储边缘数据，表示V和H计数器控制脉冲的数量应该改变其逻辑电平。 当V和H计数器的计数与边缘数据匹配时，V和H比较器和组合逻辑电路改变控制脉冲的逻辑电平。 比较器和逻辑电路还作为定时脉冲输出由时间序列数据表示的输出脉冲序列执行的逻辑运算和控制脉冲的结果。

    Storage system
    9.
    发明授权
    Storage system 失效
    存储系统

    公开(公告)号：US5070444A

    公开(公告)日：1991-12-03

    申请号：US562255

    申请日：1990-08-03

    申请人： Kanji Kubo ,  Akio Yamamoto ,  Katsumi Takeda

    发明人： Kanji Kubo ,  Akio Yamamoto ,  Katsumi Takeda

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0851

    摘要： In a storage system having a main storage and a buffer storage accessable by a plurality of requesters, the buffer storage comprises a buffer storage data area having a plurality of storage areas for storing a portion of data of the main storage as a copy of the main storage for each predetermind storage unit, and a buffer storage addess area for storing addresses of the predetermined storage units coresponding to the storage areas. The buffer storage address area is divided into a plurality of addres area banks each interleaved by storage unit, and the buffer storage data area is divided into a plurality of data area banks each interleaved by an access width unit.

    Storage system
    10.
    发明授权
    Storage system 失效
    存储系统

    公开(公告)号：US4949244A

    公开(公告)日：1990-08-14

    申请号：US148859

    申请日：1988-01-27

    申请人： Kanji Kubo ,  Akio Yamamoto ,  Katsumi Takeda

    发明人： Kanji Kubo ,  Akio Yamamoto ,  Katsumi Takeda

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0851

    摘要： In a storage system having a main storage and a buffer storage accessable by a plurality of requesters, the buffer storage comprises a buffer storage data area having a plurality of storage areas for storing a portion of data of the main storage as a copy of the main storage for each predetermined storage unit, and a buffer storage address area for storing addresses of the predetermined storage units corresponding to the storage areas. The buffer storage address area is divided into a plurality of address area banks each interleaved by storage unit, and the buffer storage data area is divided into a plurality of data area banks each interleaved by an access width unit.