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    Manufacturing method of semiconductor device with element isolation region formed within
    1.
    发明授权
    Manufacturing method of semiconductor device with element isolation region formed within 有权
    在其内形成元件隔离区的半导体器件的制造方法

    公开(公告)号：US08513072B2

    公开(公告)日：2013-08-20

    申请号：US12968656

    申请日：2010-12-15

    申请人： Shunpei Yamazaki ,  Yasuyuki Arai ,  Ikuko Kawamata

    发明人： Shunpei Yamazaki ,  Yasuyuki Arai ,  Ikuko Kawamata

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11546 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/1255 ,  H01L29/66825 ,  H01L29/7881

    摘要： In order to form a plurality of semiconductor elements over an insulating surface, in one continuous semiconductor layer, an element region serving as a semiconductor element and an element isolation region having a function to electrically isolate element regions from each other by repetition of PN junctions. The element isolation region is formed by selective addition of an impurity element of at least one or more kinds of oxygen, nitrogen, and carbon and an impurity element that imparts an opposite conductivity type to that of the adjacent element region in order to electrically isolate elements from each other in one continuous semiconductor layer.

    摘要翻译： 为了在绝缘表面上形成多个半导体元件，在一个连续半导体层中，用作半导体元件的元件区域和具有通过重复PN结将元件区域彼此电隔离的功能的元件隔离区域。 通过选择性地添加至少一种或多种氧，氮和碳的杂质元素和赋予与相邻元件区相反的导电类型的杂质元素来形成元件隔离区域，以便电隔离元件 在一个连续的半导体层中彼此相交。

    Method for manufacturing semiconductor device
    3.
    发明申请
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20080242051A1

    公开(公告)日：2008-10-02

    申请号：US12076147

    申请日：2008-03-14

    申请人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

    发明人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

    IPC分类号： H01L21/30

    CPC分类号： H01L21/76254 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

    摘要： When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.

    摘要翻译： 当单晶半导体层从单晶半导体衬底（接合晶片）转置时，选择性地蚀刻单晶半导体衬底（该步骤也称为沟槽处理），并且多个单晶半导体层是 被分割成制造的半导体元件的尺寸，被转置到不同的基板（基底）。 因此，可以在基底基板上形成多个岛状单晶半导体层（SOI层）。 此外，对形成在基底基板上的单晶半导体层进行蚀刻，并且通过加工和改进来精确地控制SOI层的形状。

    Semiconductor device, and manufacturing method of semiconductor device
    4.
    发明申请
    Semiconductor device, and manufacturing method of semiconductor device 有权
    半导体器件及半导体器件的制造方法

    公开(公告)号：US20070252209A1

    公开(公告)日：2007-11-01

    申请号：US11785965

    申请日：2007-04-23

    申请人： Shunpei Yamazaki ,  Yasuyuki Arai ,  Ikuko Kawamata

    发明人： Shunpei Yamazaki ,  Yasuyuki Arai ,  Ikuko Kawamata

    IPC分类号： H01L27/12

    CPC分类号： H01L27/11546 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/1255 ,  H01L29/66825 ,  H01L29/7881

    摘要： In order to form a plurality of semiconductor elements over an insulating surface, in one continuous semiconductor layer, an element region serving as a semiconductor element and an element isolation region having a function to electrically isolate element regions from each other by repetition of PN junctions. The element isolation region is formed by selective addition of an impurity element of at least one or more kinds of oxygen, nitrogen, and carbon and an impurity element that imparts an opposite conductivity type to that of the adjacent element region in order to electrically isolate elements from each other in one continuous semiconductor layer.

    摘要翻译： 为了在绝缘表面上形成多个半导体元件，在一个连续半导体层中，用作半导体元件的元件区域和具有通过重复PN结将元件区域彼此电隔离的功能的元件隔离区域。 通过选择性地添加至少一种或多种氧，氮和碳的杂质元素和赋予与相邻元件区相反的导电类型的杂质元素来形成元件隔离区域，以电隔离元件 在一个连续的半导体层中彼此相交。

    Display device
    7.
    发明授权
    Display device 有权
    显示设备

    公开(公告)号：US07947981B2

    公开(公告)日：2011-05-24

    申请号：US12013796

    申请日：2008-01-14

    申请人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

    发明人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

    IPC分类号： H01L29/04

    CPC分类号： H01L27/12 ,  G02F1/1345 ,  G02F1/13454 ,  H01L27/1233 ,  H01L29/78621

    摘要： It is an object to provide a display device including a thin film transistor which can operate at high speed and is driven at a low voltage in a drive circuit region, and a thin film transistor having high voltage-resistance and high reliability in a pixel region. Accordingly, it is an object to provide a high reliable display device which consumes less power. A display device including a pixel region and a drive circuit region over a substrate having an insulating surface is provided. A thin film transistor is provided in each of the pixel region and the drive circuit region. A channel formation region in a semiconductor layer of the thin film transistor provided in the drive circuit region is formed to be locally thin, and the thickness of the channel formation region is smaller than that in the pixel region.

    摘要翻译： 本发明的目的是提供一种显示装置，其包括可以在驱动电路区域中以高速操作并以低电压驱动的薄膜晶体管，以及在像素区域中具有高电压和高可靠性的薄膜晶体管 。 因此，本发明的目的是提供一种消耗较少功率的高可靠性显示装置。 提供一种显示装置，其包括具有绝缘表面的基板上的像素区域和驱动电路区域。 在像素区域和驱动电路区域的每一个中设置薄膜晶体管。 设置在驱动电路区域中的薄膜晶体管的半导体层中的沟道形成区域局部变薄，并且沟道形成区域的厚度小于像素区域中的沟道形成区域。

    Method for manufacturing semiconductor device
    9.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07811884B2

    公开(公告)日：2010-10-12

    申请号：US12692790

    申请日：2010-01-25

    申请人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

    发明人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76254 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

    摘要： When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.

    摘要翻译： 当单晶半导体层从单晶半导体衬底（接合晶片）转置时，选择性地蚀刻单晶半导体衬底（该步骤也称为沟槽处理），并且多个单晶半导体层是 被分割成制造的半导体元件的尺寸，被转置到不同的基板（基底）。 因此，可以在基底基板上形成多个岛状单晶半导体层（SOI层）。 此外，对形成在基底基板上的单晶半导体层进行蚀刻，并且通过加工和改进来精确地控制SOI层的形状。