公开(公告)号：US5938751A

公开(公告)日：1999-08-17

申请号：US912092

申请日：1997-08-15

申请人： Siamak Tavallaei ,  Joseph P. Miller

发明人： Siamak Tavallaei ,  Joseph P. Miller

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4081

摘要： A bus ring-back and voltage over-shoot reduction apparatus with capability for rendering an expansion slot of a computer system hot-pluggable, wherein a logic gate controls a switching element so that when the element is turned on, the input and output (I/O) nodes of the element are in a low ohmic conductive relationship. One of the I/O nodes is coupled to an expansion card whereas the other node is coupled to a bus to which the expansion slot is connected. The apparatus operates as a level shifter wherein the output node voltage follows the input node voltage until pinch-off such that the output voltage remains substantially stable thereafter. The apparatus also isolates the expansion card from the bus when the system is running or during the powering up of the card.

摘要翻译： 一种具有能够呈现计算机系统的可插拔的计算机系统的扩展槽的总线环回和电压过拍还原装置，其中逻辑门控制开关元件，使得当元件被接通时，输入和输出（I / O）节点处于低欧姆导电关系。 I / O节点中的一个耦合到扩展卡，而另一个节点耦合到扩展槽连接到的总线。 该装置作为电平转换器工作，其中输出节点电压跟随输入节点电压直到夹断，使得输出电压在此之后保持基本稳定。 当系统运行或卡上电时，该设备还将扩展卡与总线隔离开来。

公开(公告)号：US6032271A

公开(公告)日：2000-02-29

申请号：US658750

申请日：1996-06-05

申请人： Alan L. Goodrum ,  Jeffrey S. Autor ,  Paul R. Culley ,  Joseph P. Miller ,  Siamak Tavallaei ,  Barry P. Basile ,  Elizabeth A. Richard ,  Eric E. Rose

发明人： Alan L. Goodrum ,  Jeffrey S. Autor ,  Paul R. Culley ,  Joseph P. Miller ,  Siamak Tavallaei ,  Barry P. Basile ,  Elizabeth A. Richard ,  Eric E. Rose

IPC分类号： G06F11/30 ,  G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F11/22 ,  G06F11/267 ,  G06F11/34

CPC分类号： G06F11/2005 ,  G06F11/2007 ,  G06F11/2012 ,  G06F11/2221 ,  G06F11/349 ,  G06F11/0757 ,  G06F11/10 ,  G06F11/221

摘要： A device causing a faulty condition in a computer system having devices is isolated by detecting for a faulty condition associated with the devices and identifying the device causing the faulty condition. The devices are coupled to a bus. The faulty condition includes a bus hang condition. The devices are turned off when a bus hang condition is detected. The devices are then turned back on to test the devices. Each device is tested by writing and reading its configuration space. Information on the bus associated with the faulty condition is stored. The stored information is retrieved after the faulty condition has occurred, with the stored information including address, data, and bus control information.

摘要翻译： 在具有设备的计算机系统中导致故障状态的设备通过检测与设备相关联的故障状况并识别导致故障状态的设备而被隔离。 这些设备耦合到总线。 故障状况包括总线挂起状况。 当检测到总线挂起状态时，这些设备被关闭。 然后将设备重新打开以测试设备。 每个设备都通过写入和读取其配置空间进行测试。 存储与故障条件相关的总线上的信息。 存储的信息在故障状态发生后被检索，存储的信息包括地址，数据和总线控制信息。

公开(公告)号：US6000040A

公开(公告)日：1999-12-07

申请号：US739687

申请日：1996-10-29

申请人： Paul R. Culley ,  Joseph P. Miller ,  Daniel S. Hull ,  Siamak Tavallaei

发明人： Paul R. Culley ,  Joseph P. Miller ,  Daniel S. Hull ,  Siamak Tavallaei

IPC分类号： G06F11/22 ,  G06F11/07 ,  G06F11/00

CPC分类号： G06F11/0745 ,  G06F11/0748 ,  G06F11/079

摘要： Faults in a computer system having circuits are managed by fault detectors connected to detect fault states of respective circuits. A fault manager associates the fault states with the respective circuits. The fault manager includes a system manager connected to identify which of the circuits is causing faulty operation in the computer system. The fault detectors associated with the respective circuits are configured to detect faulty operation of and to generate fault state information for the respective circuits. A central manager is connected to accumulate fault state information from the fault detectors. One of the circuits includes a bus, and the fault state includes a bus error condition. The bus is connected to multiple devices, and the fault manager identifies which of the multiple devices causes the bus error condition. One of the circuits includes multiple modules, and the fault manager identifies fault states of the multiple modules. The modules include state machines. One of the circuits includes an internal clock, and the fault state of the circuit includes the internal clock not functioning properly. One of the circuits includes a temperature sensor, and the fault state of the circuit includes a high temperature condition detected by the temperature sensor.

摘要翻译： 具有电路的计算机系统中的故障由连接的故障检测器来管理，以检测各个电路的故障状态。 故障管理器将故障状态与相应的电路相关联。 故障管理器包括连接到系统管理器以识别哪些电路在计算机系统中导致故障的操作。 与相应电路相关联的故障检测器被配置为检测各个电路的故障操作并产生故障状态信息。 连接中央管理器，从故障检测器累积故障状态信息。 其中一个电路包括总线，故障状态包括总线错误状况。 总线连接到多个设备，故障管理器识别多个设备中的哪一个引起总线错误状况。 其中一个电路包括多个模块，故障管理器识别多个模块的故障状态。 模块包括状态机。 其中一个电路包括内部时钟，并且电路的故障状态包括内部时钟不能正常工作。 其中一个电路包括温度传感器，并且电路的故障状态包括由温度传感器检测的高温条件。

公开(公告)号：US5797018A

公开(公告)日：1998-08-18

申请号：US568478

申请日：1995-12-07

申请人： Siamak Tavallaei ,  Joseph P. Miller

发明人： Siamak Tavallaei ,  Joseph P. Miller

IPC分类号： G06F13/362 ,  G06F13/14

CPC分类号： G06F13/362

摘要： Circuitry for tristating the address and data outputs of a processor to prevent a deadlock condition when the processor and another bus master is accessing a shared resource. The processor is located on a local bus and the other bus master is located on a PCI bus. Bi-directional tristate buffers are placed between the address and data output pins of the processor and the address and data portions of the first bus. If the processor is requesting a local-bus-to-PCI-bus cycle, and the PCI bus master is asserting a request for a local bus shared resource, the processor address and data output pins are tristated by the tristate buffers to allow the PCI bus master cycle to proceed. After the PCI bus master cycle completes, the tristate buffers are reenabled to allow the processor cycle to complete.

摘要翻译： 用于调整处理器的地址和数据输出的电路，以防止处理器和另一个总线主机访问共享资源时出现死锁状况。 处理器位于本地总线上，另一个总线主机位于PCI总线上。 双向三态缓冲器被放置在处理器的地址和数据输出引脚与第一总线的地址和数据部分之间。 如果处理器正在请求本地总线到PCI总线周期，并且PCI总线主机正在确定对本地总线共享资源的请求，则处理器地址和数据输出引脚由三态缓冲器三态以允许PCI 总线主站周期进行。 PCI总线主机周期完成后，三态缓冲区将重新启用，以使处理器周期完成。

公开(公告)号：US06554654B1

公开(公告)日：2003-04-29

申请号：US10039161

申请日：2001-12-31

申请人： D. Joseph Stoddard ,  Joseph P. Miller ,  Mitchel Wright

发明人： D. Joseph Stoddard ,  Joseph P. Miller ,  Mitchel Wright

IPC分类号： H01R1324

CPC分类号： H01R13/2471 ,  H01R12/714 ,  H01R12/721 ,  H01R13/2428 ,  H05K3/366 ,  H05K3/403 ,  H05K3/429 ,  H05K2201/09145 ,  H05K2201/09181 ,  H05K2201/10303 ,  H05K2201/10424

摘要： A multi-pin edge connector assembly for connecting a daughter board to a mother board, for example, comprises a plurality of vias with conductive surfaces that are formed in the daughter board adjacent a connection edge. A plurality of openings are also formed in the daughter board, with each opening extending from the connection edge to one of the vias. Electrically conductive pins are positioned in the openings, with each pin having a first end in electrical contact with one of the conductive surfaces and a second end that projects beyond the connection edge for electrically contacting conductive pads or surfaces on the mother board. A retainer is mounted to the daughter board for holding the pins in their respective openings.

摘要翻译： 例如，用于将子板连接到母板的多引脚边缘连接器组件包括多个通孔，导电表面形成在邻接连接边缘的子板中。 在子板中还形成有多个开口，每个开口从连接边缘延伸到其中一个通孔。 导电销定位在开口中，每个销具有与导电表面中的一个电接触的第一端和突出超过连接边缘的第二端，用于电接触母板上的导电垫或表面。 保持器安装到子板，用于将销保持在它们各自的开口中。

公开(公告)号：US5809186A

公开(公告)日：1998-09-15

申请号：US905813

申请日：1997-07-31

申请人： Joseph P. Miller

发明人： Joseph P. Miller

IPC分类号： G02B6/12 ,  G02B6/30 ,  G02B6/42 ,  G02F1/065 ,  G02F1/313

CPC分类号： G02B6/12004 ,  G02F1/3132 ,  G02B2006/12069 ,  G02B2006/12145 ,  G02B2006/12147 ,  G02B6/30 ,  G02B6/4249 ,  G02F1/065

摘要： Electrical signals are received corresponding to sets of digital data, and output optical signals are delivered, corresponding to the digital data, on at least two optical channels corresponding to different sets of the digital data, using light from a single light source. In another scheme, the optical switch may be integrated with an optical transmission medium (e.g., an optical cable).

摘要翻译： 对应于数字数据集合接收电信号，并且使用来自单个光源的光，在对应于数字数据的不同集合的至少两个光通道上传送对应于数字数据的输出光信号。 在另一方案中，光开关可以与光传输介质（例如，光缆）集成。

公开(公告)号：US06269273B1

公开(公告)日：2001-07-31

申请号：US09098077

申请日：1998-06-16

申请人： Joseph P. Miller

发明人： Joseph P. Miller

IPC分类号： G05B1101

CPC分类号： G02B6/12004 ,  G02B6/30 ,  G02B6/4249 ,  G02B2006/12069 ,  G02B2006/12145 ,  G02B2006/12147 ,  G02F1/065 ,  G02F1/3132

摘要： Electrical signals are received corresponding to sets of digital data, and output optical signals are delivered, corresponding to the digital data, on at least two optical channels corresponding to different sets of the digital data, using light from a single light source. In another scheme, the optical switch may be integrated with an optical transmission medium (e.g., an optical cable).

摘要翻译： 对应于数字数据集合接收电信号，并且使用来自单个光源的光，在对应于数字数据的不同集合的至少两个光通道上，输出对应于数字数据的输出光信号。 在另一方案中，光开关可以与光传输介质（例如，光缆）集成。

公开(公告)号：US5822571A

公开(公告)日：1998-10-13

申请号：US659142

申请日：1996-06-05

申请人： Alan L. Goodrum ,  Jens K. Ramsey ,  Paul R. Culley ,  Joseph P. Miller

发明人： Alan L. Goodrum ,  Jens K. Ramsey ,  Paul R. Culley ,  Joseph P. Miller

IPC分类号： G06F13/36 ,  G06F1/12 ,  G06F13/40 ,  G06F13/42 ,  G06F5/06

CPC分类号： G06F13/405

摘要： Data is transmitted between a first device and a second device connected by the communications channel in a computer system. The first device generates a first clock and the second device generates a second clock. The first clock is provided to the second device and the second clock is provided to the first device. Data received by the first device over the communications channel from the second device is synchronized to the first clock. The receiving logic in the first device includes a first-in-first-out buffer The received data is stored in a first-in-first-out buffer until the data is synchronized to the first clock. The first and second clocks have the same frequency.

摘要翻译： 在计算机系统中，通过通信信道连接的第一设备和第二设备之间传送数据。 第一设备产生第一时钟，第二设备产生第二时钟。 将第一时钟提供给第二设备，并且将第二时钟提供给第一设备。 由第一设备通过通信信道从第二设备接收的数据被同步到第一时钟。 第一设备中的接收逻辑包括先进先出缓冲器。接收到的数据被存储在先进先出缓冲器中，直到数据与第一时钟同步。 第一和第二个时钟具有相同的频率。

公开(公告)号：US5134713A

公开(公告)日：1992-07-28

申请号：US354446

申请日：1989-05-19

申请人： Joseph P. Miller ,  Mark Taylor ,  Mike E. Tullis

发明人： Joseph P. Miller ,  Mark Taylor ,  Mike E. Tullis

IPC分类号： G06F9/38

CPC分类号： G06F9/3877

摘要： A latch circuit receiving the system reset signal and the error signal from a coprocessor provides an output indicating the presence of the coprocessor. The latch circuit provides the output for computer systems which cannot connect the coprocessor error signal to a coprocessor error input on the processor.

摘要翻译： 从协处理器接收系统复位信号和误差信号的锁存电路提供指示协处理器的存在的输出。 锁存电路提供不能将协处理器错误信号连接到处理器上的协处理器错误输入的计算机系统的输出。

公开(公告)号：US20120012380A1

公开(公告)日：2012-01-19

申请号：US13259081

申请日：2009-04-13

申请人： Joseph P. Miller

发明人： Joseph P. Miller

IPC分类号： H05K1/11 ,  H01K3/10

CPC分类号： H05K3/0047 ,  H05K1/0251 ,  H05K1/0268 ,  H05K3/429 ,  H05K2203/0207 ,  H05K2203/175 ,  Y10T29/49165

摘要： A back drill verification feature is provided on a layer of a circuit board. Before a back drill operation is performed, an electrical connection exists between conductive material in a via hole and the back drill verification feature. After the back drill operation, the electrical connection is severed.

摘要翻译： 在电路板的一层上提供了背面钻孔验证功能。 在执行后钻操作之前，在通孔中的导电材料和后钻钻孔验证特征之间存在电连接。 在后钻操作之后，电连接断开。