公开(公告)号：US20240112003A1

公开(公告)日：2024-04-04

申请号：US18077993

申请日：2022-12-08

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  NGHIA LE ,  HIEN PHAM

IPC: G06N3/063 ,  G06F5/01 ,  G06F7/501

CPC classification number: G06N3/063 ,  G06F5/01 ,  G06F7/501

Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.

公开(公告)号：US20210342682A1

公开(公告)日：2021-11-04

申请号：US17367633

申请日：2021-07-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STANLEY HONG ,  ANH LY ,  THUAN VU ,  HIEN PHAM ,  KHA NGUYEN ,  HAN TRAN

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

公开(公告)号：US20200342938A1

公开(公告)日：2020-10-29

申请号：US16503355

申请日：2019-07-03

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  ANH LY ,  HAN TRAN ,  KHA NGUYEN ,  HIEN PHAM

IPC: G11C11/56 ,  G11C11/16 ,  G11C11/4074 ,  G06F17/16 ,  G06N3/06

Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.

公开(公告)号：US20240095509A1

公开(公告)日：2024-03-21

申请号：US18520500

申请日：2023-11-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STANLEY HONG ,  ANH LY ,  THUAN VU ,  HIEN PHAM ,  KHA NGUYEN ,  HAN TRAN

IPC: G06N3/065 ,  G06F17/16 ,  G06N3/04

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/04

Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

公开(公告)号：US20230048411A1

公开(公告)日：2023-02-16

申请号：US17520396

申请日：2021-11-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  KHA NGUYEN ,  THUAN VU ,  HIEN PHAM ,  STANLEY HONG ,  STEPHEN TRINH

IPC: G06N3/063 ,  G06F17/16 ,  H03M1/46

Abstract: Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.

公开(公告)号：US20240282351A1

公开(公告)日：2024-08-22

申请号：US18195322

申请日：2023-05-09

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  HOA VU ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  NGHIA LE ,  DUC NGUYEN ,  HIEN PHAM

IPC: G11C7/16 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C7/16 ,  G11C7/12 ,  G11C7/14

Abstract: In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.

公开(公告)号：US20240095508A1

公开(公告)日：2024-03-21

申请号：US18520277

申请日：2023-11-27

Applicant: Silicon Storage Technology, inc.

Inventor： HIEU VAN TRAN ,  STANLEY HONG ,  AHN LY ,  THUAN VU ,  HIEN PHAM ,  KHA NGUYEN ,  HAN TRAN

IPC: G06N3/065 ,  G06F17/16 ,  G06N3/04

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/04

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.