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    Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
    1.
    发明授权
    Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same 有权
    在硅绝缘体上制造松弛的SiGe缓冲层的方法和含有该SiGe缓冲层的结构

    公开(公告)号：US06833332B2

    公开(公告)日：2004-12-21

    申请号：US10323024

    申请日：2002-12-18

    申请人： Silke H. Christiansen ,  Alfred Grill ,  Patricia M. Mooney

    发明人： Silke H. Christiansen ,  Alfred Grill ,  Patricia M. Mooney

    IPC分类号： H01L2126

    CPC分类号： H01L21/76251 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/324 ,  H01L21/76243

    摘要： A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.

    摘要翻译： 提供了一种在绝缘体上硅（SOI）衬底上制造具有低穿透位错密度的弛豫SiGe缓冲层的方法。 通过在SOI衬底的表面上外延沉积无缺陷的Stranski-Krastanov Ge或SiGe岛来制造弛豫的SiGe缓冲层; 用Si或Si富SiGe层对岛进行封盖和平面化，以及在升高的温度下对结构进行退火，直到混合，从而在初始的绝缘层（即，掩埋氧化物层）上形成松弛的SiGe层 实现了SOI晶片。 本发明还涉及至少包括上述松弛的SiGe缓冲层的半导体结构，器件和集成电路。

    Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
    3.
    发明授权
    Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing 失效
    通过离子注入和热退火，在Si或绝缘体上的衬底上放置SiGe层

    公开(公告)号：US06855649B2

    公开(公告)日：2005-02-15

    申请号：US10299880

    申请日：2002-11-19

    申请人： Silke H. Christiansen ,  Jack O. Chu ,  Alfred Grill ,  Patricia M. Mooney

    发明人： Silke H. Christiansen ,  Jack O. Chu ,  Alfred Grill ,  Patricia M. Mooney

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L21/00

    CPC分类号： H01L21/26506 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/7624 ,  H01L21/76251 ,  Y10S438/933

    摘要： A method to obtain thin (less than 300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 106 cm2. The approach begins with the growth of a pseudomorphic or nearly pseudomorphic Si1-xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

    摘要翻译： 在Si或绝缘体上硅（SOI）衬底上获得薄（小于300nm）应变弛豫Si1-xGex缓冲层的方法。 这些缓冲层具有失配位错的均匀分布，其缓解了应变，表面光滑平滑，以及低穿透位错（TD）密度，即小于10 6 cm 2。 该方法开始于伪晶体或近似伪晶Si1-xGex层的生长，即，不具有失配位错的层，然后将其注入He或其它轻元素，随后退火以实现显着的应变弛豫。 使用该方法操作的非常有效的应变松弛机理是在Si引起的平行于Si（001）表面的Si / Si1-xGex界面下面的He诱导的血小板（不是气泡）处的位错成核。

    Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
    5.
    发明授权
    Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same 有权
    在硅绝缘体上制造松弛的SiGe缓冲层的方法和含有该SiGe缓冲层的结构

    公开(公告)号：US06515335B1

    公开(公告)日：2003-02-04

    申请号：US10037611

    申请日：2002-01-04

    申请人： Silke H. Christiansen ,  Alfred Grill ,  Patricia M. Mooney

    发明人： Silke H. Christiansen ,  Alfred Grill ,  Patricia M. Mooney

    IPC分类号： H01L31392

    CPC分类号： H01L21/76251 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/324 ,  H01L21/76243

    摘要： A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.

    摘要翻译： 提供了一种在绝缘体上硅（SOI）衬底上制造具有低穿透位错密度的弛豫SiGe缓冲层的方法。 通过在SOI衬底的表面上外延沉积无缺陷的Stranski-Krastanov Ge或SiGe岛来制造弛豫的SiGe缓冲层; 用Si或Si富SiGe层对岛进行封盖和平面化，以及在升高的温度下对结构进行退火，直到混合，从而在初始的绝缘层（即，掩埋氧化物层）上形成松弛的SiGe层 实现了SOI晶片。 本发明还涉及至少包括上述松弛的SiGe缓冲层的半导体结构，器件和集成电路。