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    Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
    3.
    发明授权
    Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing 失效
    通过离子注入和热退火，在Si或绝缘体上的衬底上放置SiGe层

    公开(公告)号：US06855649B2

    公开(公告)日：2005-02-15

    申请号：US10299880

    申请日：2002-11-19

    申请人： Silke H. Christiansen ,  Jack O. Chu ,  Alfred Grill ,  Patricia M. Mooney

    发明人： Silke H. Christiansen ,  Jack O. Chu ,  Alfred Grill ,  Patricia M. Mooney

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L21/00

    CPC分类号： H01L21/26506 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/7624 ,  H01L21/76251 ,  Y10S438/933

    摘要： A method to obtain thin (less than 300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 106 cm2. The approach begins with the growth of a pseudomorphic or nearly pseudomorphic Si1-xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

    摘要翻译： 在Si或绝缘体上硅（SOI）衬底上获得薄（小于300nm）应变弛豫Si1-xGex缓冲层的方法。 这些缓冲层具有失配位错的均匀分布，其缓解了应变，表面光滑平滑，以及低穿透位错（TD）密度，即小于10 6 cm 2。 该方法开始于伪晶体或近似伪晶Si1-xGex层的生长，即，不具有失配位错的层，然后将其注入He或其它轻元素，随后退火以实现显着的应变弛豫。 使用该方法操作的非常有效的应变松弛机理是在Si引起的平行于Si（001）表面的Si / Si1-xGex界面下面的He诱导的血小板（不是气泡）处的位错成核。

    Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
    4.
    发明授权
    Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same 有权
    在硅绝缘体上制造松弛的SiGe缓冲层的方法和含有该SiGe缓冲层的结构

    公开(公告)号：US06515335B1

    公开(公告)日：2003-02-04

    申请号：US10037611

    申请日：2002-01-04

    申请人： Silke H. Christiansen ,  Alfred Grill ,  Patricia M. Mooney

    发明人： Silke H. Christiansen ,  Alfred Grill ,  Patricia M. Mooney

    IPC分类号： H01L31392

    CPC分类号： H01L21/76251 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/324 ,  H01L21/76243

    摘要： A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.

    摘要翻译： 提供了一种在绝缘体上硅（SOI）衬底上制造具有低穿透位错密度的弛豫SiGe缓冲层的方法。 通过在SOI衬底的表面上外延沉积无缺陷的Stranski-Krastanov Ge或SiGe岛来制造弛豫的SiGe缓冲层; 用Si或Si富SiGe层对岛进行封盖和平面化，以及在升高的温度下对结构进行退火，直到混合，从而在初始的绝缘层（即，掩埋氧化物层）上形成松弛的SiGe层 实现了SOI晶片。 本发明还涉及至少包括上述松弛的SiGe缓冲层的半导体结构，器件和集成电路。

    Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
    5.
    发明授权
    Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same 有权
    在硅绝缘体上制造松弛的SiGe缓冲层的方法和含有该SiGe缓冲层的结构

    公开(公告)号：US06833332B2

    公开(公告)日：2004-12-21

    申请号：US10323024

    申请日：2002-12-18

    申请人： Silke H. Christiansen ,  Alfred Grill ,  Patricia M. Mooney

    发明人： Silke H. Christiansen ,  Alfred Grill ,  Patricia M. Mooney

    IPC分类号： H01L2126

    CPC分类号： H01L21/76251 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/324 ,  H01L21/76243

    摘要： A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.

    摘要翻译： 提供了一种在绝缘体上硅（SOI）衬底上制造具有低穿透位错密度的弛豫SiGe缓冲层的方法。 通过在SOI衬底的表面上外延沉积无缺陷的Stranski-Krastanov Ge或SiGe岛来制造弛豫的SiGe缓冲层; 用Si或Si富SiGe层对岛进行封盖和平面化，以及在升高的温度下对结构进行退火，直到混合，从而在初始的绝缘层（即，掩埋氧化物层）上形成松弛的SiGe层 实现了SOI晶片。 本发明还涉及至少包括上述松弛的SiGe缓冲层的半导体结构，器件和集成电路。

    Carbon-on-insulator substrates by in-place bonding
    7.
    发明授权
    Carbon-on-insulator substrates by in-place bonding 失效
    通过就地键合在绝缘体上的基板上

    公开(公告)号：US07811906B1

    公开(公告)日：2010-10-12

    申请号：US12612331

    申请日：2009-11-04

    申请人： Ageeth A. Bol ,  Jack O. Chu ,  Alfred Grill ,  Conal E. Murray ,  Katherine L. Saenger

    发明人： Ageeth A. Bol ,  Jack O. Chu ,  Alfred Grill ,  Conal E. Murray ,  Katherine L. Saenger

    IPC分类号： H01L21/36 ,  H01L21/20 ,  H01L21/44 ,  H01L21/31

    CPC分类号： H01L21/32139 ,  H01L21/762

    摘要： An in-place bonding method in which a metal template layer under a carbon layer is removed while the carbon layer is still attached to a substrate is described for forming a carbon-on-insulator substrate. In one embodiment of the in-place bonding method, at least one layered metal/carbon (M/C) region is formed on an insulating surface layer of an initial substrate structure. The at least one layered M/C region has edges that are bordered by exposed regions of the insulating surface layer. Some edges of the at least one layered M/C region are then secured to a base substrate of the initial structure via a securing structure, while other edges are left exposed. A selective metal etchant removes the metal layer under the carbon layer using the exposed edges for access. After metal etching, the now-unsupported carbon layer bonds to the underlying insulating surface layer by attraction.

    摘要翻译： 为了形成绝缘体上的基板，描述了其中在碳层仍然附着到基板上时除去碳层下面的金属模板层的就地结合方法。 在就地接合方法的一个实施例中，在初始衬底结构的绝缘表面层上形成至少一个层状金属/碳（M / C）区域。 所述至少一层分层的M / C区域具有与绝缘表面层的暴露区域相邻的边缘。 然后，至少一层分层M / C区域的一些边缘经由固定结构固定到初始结构的基底，同时其它边缘被暴露。 选择性金属蚀刻剂使用暴露的边缘去除碳层下方的金属层以进入。 在金属蚀刻之后，现在无载体的碳层通过吸引而结合到下面的绝缘表面层。

    Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector
    8.
    发明授权
    Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector 有权
    制造高速CMOS兼容的绝缘体上的光电探测器的结构和方法

    公开(公告)号：US07510904B2

    公开(公告)日：2009-03-31

    申请号：US11556739

    申请日：2006-11-06

    申请人： Jack O. Chu ,  Gabriel K. Dehlinger ,  Alfred Grill ,  Steven J. Koester ,  Qiqing Ouyang ,  Jeremy D. Schaub

    发明人： Jack O. Chu ,  Gabriel K. Dehlinger ,  Alfred Grill ,  Steven J. Koester ,  Qiqing Ouyang ,  Jeremy D. Schaub

    IPC分类号： H01L21/00

    CPC分类号： H01L31/101

    摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

    摘要翻译： 本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。 该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。 该器件通过利用掩埋绝缘层，通过利用Ge吸收层，利用薄的吸收层和窄电极间隔的低电压操作以及兼容性来兼容宽泛的光谱，利用埋入的绝缘层来隔离底层衬底中产生的载流子， 通过其平面结构和使用IV族吸收材料的CMOS器件。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。 该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。

    Graphene growth on a non-hexagonal lattice
    9.
    发明授权
    Graphene growth on a non-hexagonal lattice 有权
    非六方晶格上的石墨烯生长

    公开(公告)号：US08877340B2

    公开(公告)日：2014-11-04

    申请号：US12844029

    申请日：2010-07-27

    申请人： Jack O. Chu ,  Christos Dimitrakopoulos ,  Marcus O. Freitag ,  Alfred Grill ,  Timothy J. McArdle ,  Chun-Yung Sung ,  Robert L. Wisnieff

    发明人： Jack O. Chu ,  Christos Dimitrakopoulos ,  Marcus O. Freitag ,  Alfred Grill ,  Timothy J. McArdle ,  Chun-Yung Sung ,  Robert L. Wisnieff

    IPC分类号： B32B9/00

    CPC分类号： H01L21/02527 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/188 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02516 ,  Y10T428/30

    摘要： A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.

    摘要翻译： 在具有非六边形对称性的结晶表面上形成石墨烯层。 晶体表面可以是单晶半导体碳化物层的表面。 单晶半导体碳化物层的非六边形对称表面在超高真空环境中在升高的温度下退火以形成石墨烯层。 在退火过程中，单晶半导体碳化物层的非六边形表面上的半导体原子对碳原子有选择性的蒸发。 随着半导体原子被选择性地去除，半导体 - 碳合金层表面上的碳浓度增加。 尽管半导体 - 碳合金层的表面具有非六边形对称性，但剩余的碳原子可以聚结形成具有六边形对称性的石墨烯层。

    Graphene growth on a carbon-containing semiconductor layer
    10.
    发明授权
    Graphene growth on a carbon-containing semiconductor layer 有权
    含碳半导体层上的石墨烯生长

    公开(公告)号：US08187955B2

    公开(公告)日：2012-05-29

    申请号：US12546034

    申请日：2009-08-24

    申请人： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  Chun-yung Sung

    发明人： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  Chun-yung Sung

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L29/1606 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/184 ,  C01B2204/04 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/02667 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/161 ,  Y10T428/265

    摘要： A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.

    摘要翻译： 半导体 - 碳合金层形成在半导体衬底的表面上，半导体衬底的表面可以是诸如硅衬底的市售半导体衬底。 半导体 - 碳合金层在高温退火期间被转化为至少一个石墨烯层，在此期间半导体 - 碳合金层表面上的半导体材料对碳原子有选择性的蒸发。 随着半导体原子被选择性地去除并且半导体 - 碳合金层的表面上的碳浓度增加，半导体 - 碳合金层顶层中剩余的碳原子聚结形成具有至少一个石墨烯单层的石墨烯层 。 因此，可以在直径为200mm或300mm的市售半导体衬底上提供石墨烯层。