公开(公告)号：US09076820B2

公开(公告)日：2015-07-07

申请号：US13600373

申请日：2012-08-31

申请人： Soichiro Kitazaki ,  Masaru Kidoh ,  Mitsuru Sato ,  Ryota Katsumata ,  Tadashi Iguchi

发明人： Soichiro Kitazaki ,  Masaru Kidoh ,  Mitsuru Sato ,  Ryota Katsumata ,  Tadashi Iguchi

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7827

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of insulating isolation sections provided so as to extend in a first direction, isolate the stacked body in a second direction, and have a projection projecting from the stacked body. Each insulating isolation section has a side wall including recessed sections and projected sections repeated along the first direction. The method includes forming a sidewall film on a side wall of the projection of the insulating isolation section, and forming a plurality of first holes surrounded by the sidewall film and isolated by the sidewall film in the first direction, between the plurality of insulating isolation sections. The method includes forming a second hole in the stacked body provided under the first hole by etching with the insulating isolation section and the sidewall film used as a mask.

摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括形成多个绝缘隔离部分，其被设置为沿第一方向延伸，使堆叠体沿第二方向隔离，并具有从堆叠体突出的突出部。 每个绝缘隔离部分具有侧壁，该侧壁包括沿着第一方向重复的凹陷部分和突出部分。 该方法包括在绝缘隔离部分的突起的侧壁上形成侧壁膜，并且在多个绝缘隔离部分之间形成由侧壁膜围绕并由第一方向隔离的多个第一孔 。 该方法包括通过用绝缘隔离部分和用作掩模的侧壁膜进行蚀刻，在设置在第一孔下方的层叠体中形成第二孔。

公开(公告)号：US08436416B2

公开(公告)日：2013-05-07

申请号：US12839784

申请日：2010-07-20

申请人： Daigo Ichinose ,  Tadashi Iguchi

发明人： Daigo Ichinose ,  Tadashi Iguchi

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  H01L27/11575 ,  H01L27/11582

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a plurality of semiconductor pillars and a charge storage film. The stacked body is provided on the substrate, with a plurality of insulating films alternately stacked with a plurality of electrode films, and includes a hydrophobic layer provided between one of the insulating films and one of the electrode films. The hydrophobic layer has higher hydrophobicity than the electrode films. The plurality of semiconductor pillars extend in a stacking direction of the stacked body and pierce the stacked body, and the charge storage film is provided between the electrode films and one of the semiconductor pillars.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括衬底，层叠体，多个半导体柱和电荷存储膜。 层叠体设置在基板上，多个绝缘膜交替地堆叠有多个电极膜，并且包括设置在绝缘膜之一和一个电极膜之间的疏水层。 疏水层具有比电极膜更高的疏水性。 多个半导体柱沿堆叠体的堆叠方向延伸并刺穿层叠体，并且电荷存储膜设置在电极膜和一个半导体柱之间。

公开(公告)号：US08247860B2

公开(公告)日：2012-08-21

申请号：US12646684

申请日：2009-12-23

申请人： Masao Iwase ,  Tadashi Iguchi

发明人： Masao Iwase ,  Tadashi Iguchi

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes: a substrate; a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the stacked body being provided on the substrate and having a step in its end portion for each of the electrode films; an interlayer dielectric film burying the end portion of the stacked body; a plurality of semiconductor pillars extending in the stacking direction of the stacked body and penetrating through a center portion of the stacked body; a charge storage layer provided between one of the electrode films and one of the semiconductor pillars; and a plug buried in the interlayer dielectric film and connected to a portion of each of the electrode films constituting the step, a portion of each of the dielectric films in the center portion having a larger thickness than a portion of each of the dielectric films in the end portion.

摘要翻译： 非易失性半导体存储器件包括：衬底; 具有交替层叠的多个电介质膜和电极膜的层叠体，所述层叠体设置在所述基板上，并且在其每个所述电极膜的​​端部具有台阶; 掩埋层叠体的端部的层间绝缘膜; 多个半导体柱，沿堆叠体的层叠方向延伸并穿过层叠体的中心部; 设置在所述电极膜之一和所述半导体柱之一中的电荷存储层; 以及埋在层间电介质膜中并与构成该台阶的各电极膜的一部分连接的插头，中央部的各电介质膜的一部分的厚度比电介质膜的各部分的厚度大 端部。

公开(公告)号：US08241984B2

公开(公告)日：2012-08-14

申请号：US12917689

申请日：2010-11-02

申请人： Masao Iwase ,  Tadashi Iguchi

发明人： Masao Iwase ,  Tadashi Iguchi

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11548

摘要： A semiconductor device including a semiconductor substrate, and a memory cell and a peripheral circuit provided on the semiconductor substrate, the memory cell having a first insulating film, a first electrode layer, a second insulating film, and a second electrode layer provided on the semiconductor substrate in order, and the peripheral circuit having the first insulating film, the first electrode layer, the second insulating film having an opening for the peripheral circuit, and the second electrode layer electrically connected to the first electrode layer through the opening for the peripheral circuit, wherein a thickness of the first electrode layer under the second insulating film of the peripheral circuit is thicker than a thickness of the first electrode layer of the memory cell.

摘要翻译： 一种半导体器件，包括半导体衬底，以及设置在半导体衬底上的存储单元和外围电路，所述存储单元具有第一绝缘膜，第一电极层，第二绝缘膜和设置在半导体上的第二电极层 基板，并且具有第一绝缘膜的外围电路，第一电极层，具有用于外围电路的开口的第二绝缘膜，以及通过外围电路的开口与第一电极层电连接的第二电极层 其中，外围电路的第二绝缘膜下面的第一电极层的厚度比存储单元的第一电极层的厚度厚。

公开(公告)号：US07915156B2

公开(公告)日：2011-03-29

申请号：US12391953

申请日：2009-02-24

申请人： Kenji Aoyama ,  Eiji Ito ,  Masahiro Kiyotoshi ,  Tadashi Iguchi ,  Moto Yabuki

发明人： Kenji Aoyama ,  Eiji Ito ,  Masahiro Kiyotoshi ,  Tadashi Iguchi ,  Moto Yabuki

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/764 ,  H01L29/66825

摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

摘要翻译： 半导体存储器件具有半导体衬底，在半导体衬底上以预定间隔形成的多个字线，每个字线具有栅极绝缘膜，电荷存储层，第一绝缘膜和控制栅电极，它们被堆叠 并且包括位于栅极绝缘膜的高度之上的金属氧化物层，覆盖字线的一侧的第二绝缘膜和字线之间的半导体衬底的表面，并且具有15nm的膜厚度或 并且形成在彼此相邻的字线之间的第三绝缘膜，使得低于金属氧化物层的电平的区域具有空腔。

公开(公告)号：US07582928B2

公开(公告)日：2009-09-01

申请号：US11833276

申请日：2007-08-03

申请人： Tadashi Iguchi ,  Yoshiaki Himeno ,  Hiroaki Tsunoda

发明人： Tadashi Iguchi ,  Yoshiaki Himeno ,  Hiroaki Tsunoda

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825

摘要： A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

摘要翻译： 旨在防止由浮动栅极之间的电荷的移动引起的数据破坏，从而提高可靠性的非易失性半导体存储器件包括埋入硅衬底中以隔离条形元件形成区域的元件隔离/绝缘膜。 经由第一栅极绝缘膜形成在衬底区域浮动栅极上，并且还经由第二栅极绝缘膜形成控制栅极。 源极和漏极扩散层与控制栅极自对准地形成。 浮动栅极上的第二栅极绝缘膜通过在元件隔离/绝缘膜上方的狭缝与浮动栅极分开并分离成各个存储单元的离散部分。

公开(公告)号：US20090057749A1

公开(公告)日：2009-03-05

申请号：US12188617

申请日：2008-08-08

申请人： Kenji GOMIKAWA ,  Tadashi Iguchi ,  Mitsuhiro Noguchi ,  Shoichi Watanabe

发明人： Kenji GOMIKAWA ,  Tadashi Iguchi ,  Mitsuhiro Noguchi ,  Shoichi Watanabe

IPC分类号： H01L29/00

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

摘要翻译： 存储单元包括浮置栅电极，第一电极间绝缘膜和控制栅电极。 外围晶体管包括下电极，第二电极间绝缘膜和上电极。 下电极和上电极通过设置在第二电极间绝缘膜上的开口电连接。 第一和第二电极间绝缘膜包括高电容率材料，第一电极间绝缘膜具有第一结构，第二电极间绝缘膜具有与第一结构不同的第二结构。

公开(公告)号：US07382649B2

公开(公告)日：2008-06-03

申请号：US11148336

申请日：2005-06-09

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma ,  Tadashi Iguchi ,  Hisashi Watanobe ,  Hiroaki Tsunoda

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma ,  Tadashi Iguchi ,  Hisashi Watanobe ,  Hiroaki Tsunoda

IPC分类号： G11C11/34

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.

摘要翻译： 非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第 相邻的存储单元单元阵列在行方向上排列。

公开(公告)号：US07382015B2

公开(公告)日：2008-06-03

申请号：US11094467

申请日：2005-03-31

申请人： Tadashi Iguchi ,  Yoshiaki Himeno ,  Hiroaki Tsunoda

发明人： Tadashi Iguchi ,  Yoshiaki Himeno ,  Hiroaki Tsunoda

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L29/00

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825

摘要： A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

摘要翻译： 旨在防止由浮动栅极之间的电荷的移动引起的数据破坏，从而提高可靠性的非易失性半导体存储器件包括埋入硅衬底中以隔离条形元件形成区域的元件隔离/绝缘膜。 在基板上形成有通过第一栅极绝缘膜的浮动栅极，并且还经由第二栅极绝缘膜的控制栅极。 源极和漏极扩散层与控制栅极自对准地形成。 浮动栅极上的第二栅极绝缘膜通过在元件隔离/绝缘膜上方的狭缝与浮动栅极分开并分离成各个存储单元的离散部分。

公开(公告)号：US07095093B2

公开(公告)日：2006-08-22

申请号：US10839140

申请日：2004-05-06

申请人： Tadashi Iguchi ,  Hiroaki Tsunoda ,  Koichi Matsuno

发明人： Tadashi Iguchi ,  Hiroaki Tsunoda ,  Koichi Matsuno

IPC分类号： H01L29/00

CPC分类号： H01L21/28123 ,  H01L21/28247 ,  H01L21/76224 ,  H01L21/76232

摘要： A semiconductor device comprises a semiconductor substrate having a substrate top surface on which a device should be formed; a gate electrode having an opposed surface opposed to said substrate top surface, and electrically insulated from said semiconductor substrate by a gate insulating film, a trench formed through said gate electrode into said semiconductor substrate to electrically isolate a device region for forming a device from the remainder region of said substrate top surface, a first boundary end portion, which is defined between a substrate side surface of said semiconductor substrate forming a part of the side surface of said trench and said substrate top surface, and a second boundary end portion, which is defined between a gate side surface of said gate electrode forming another part of the side surface of said trench and said opposed surface, wherein said first boundary end portion and said second boundary end portion have spherical shapes having a curvature radius not smaller than 30 angstrom.