Design method and system for optimum performance in integrated circuits that use power management
    3.
    发明授权
    Design method and system for optimum performance in integrated circuits that use power management 有权
    使用电源管理的集成电路中的最佳性能设计方法和系统

    公开(公告)号:US07216310B2

    公开(公告)日:2007-05-08

    申请号:US10993815

    申请日:2004-11-19

    CPC分类号: G06F17/505

    摘要: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

    摘要翻译: 本发明提供一种设计电路的方法(100)。 该方法包括指定(105)存储晶体管和逻辑晶体管的设计参数,并选择(110)存储晶体管的测试保持模式偏置电压。 所述方法还包括在所述测试保持模式偏置电压下确定(115)保持模式漏电流和所述设计参数的第一关系,并获得(120)所述有源模式驱动电流与所述设计参数的第二关系。 使用第一和第二关系(125)来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。 该方法还包括调整(130)测试保持模式偏置电压,并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

    Design method and system for optimum performance in integrated circuits that use power management
    4.
    发明申请
    Design method and system for optimum performance in integrated circuits that use power management 有权
    使用电源管理的集成电路中的最佳性能设计方法和系统

    公开(公告)号:US20050149887A1

    公开(公告)日:2005-07-07

    申请号:US10993815

    申请日:2004-11-19

    IPC分类号: G06F17/50

    CPC分类号: G06F17/505

    摘要: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

    摘要翻译: 本发明提供一种设计电路的方法(100)。 该方法包括指定(105)存储晶体管和逻辑晶体管的设计参数,并选择(110)存储晶体管的测试保持模式偏置电压。 所述方法还包括在所述测试保持模式偏置电压下确定(115)保持模式漏电流和所述设计参数的第一关系,并获得(120)所述有源模式驱动电流与所述设计参数的第二关系。 使用第一和第二关系(125)来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。 该方法还包括调整(130)测试保持模式偏置电压,并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

    Method and device for generating 3D panoramic video streams, and videoconference method and device
    6.
    发明授权
    Method and device for generating 3D panoramic video streams, and videoconference method and device 有权
    用于生成3D全景视频流的方法和设备,以及视频会议方法和设备

    公开(公告)号:US08717405B2

    公开(公告)日:2014-05-06

    申请号:US13172193

    申请日:2011-06-29

    IPC分类号: H04N7/14

    摘要: A method and a device for generating 3-dimensional (3D) panoramic video streams, a videoconference method, and a videoconference device are disclosed. The method includes: obtaining depth information of at least two video images; obtaining image data in multiple depth positions from a corresponding video image according to the depth information of each video image; stitching data of the video images according to the obtained image data in multiple depth positions, and generating 3D panoramic video streams. The technical solution of the present invention provides users with high-resolution 3D panoramic seamless telepresence conference video images based on different display modes of different display devices.

    摘要翻译: 公开了一种用于产生三维(3D)全景视频流的方法和装置,视频会议方法和视频会议装置。 该方法包括:获取至少两个视频图像的深度信息; 根据每个视频图像的深度信息从相应的视频图像获得多个深度位置的图像数据; 根据所获得的多个深度位置的图像数据拼接视频图像的数据,并生成3D全景视频流。 本发明的技术方案为用户提供了基于不同显示设备的不同显示模式的高分辨率3D全景无线远程呈现会议视频图像。

    Method and apparatus for processing image
    7.
    发明授权
    Method and apparatus for processing image 有权
    图像处理方法及装置

    公开(公告)号:US08355062B2

    公开(公告)日:2013-01-15

    申请号:US13189058

    申请日:2011-07-22

    IPC分类号: H04N5/262 G06K9/32

    CPC分类号: G06T15/20 G06T3/0012

    摘要: A method for processing an image includes: obtaining depth values of an image including a target region and a non-target region; obtaining a scaling ratio of the target region; obtaining a scaling ratio of the non-target region according to the depth values of the image and the scaling ratio of the target region; scaling respectively the target region and the non-target region according to the scaling ratio of the target region and the scaling ratio of the non-target region, and obtaining a scaled image.

    摘要翻译: 一种处理图像的方法包括:获得包括目标区域和非目标区域的图像的深度值; 获得目标区域的缩放比例; 根据图像的深度值和目标区域的缩放比例获得非目标区域的缩放比例; 根据目标区域的缩放比率和非目标区域的缩放比例,分别对目标区域和非目标区域进行缩放,并获得缩放图像。

    MOSFET WITH SOURCE SIDE ONLY STRESS
    8.
    发明申请
    MOSFET WITH SOURCE SIDE ONLY STRESS 有权
    MOSFET,源极只有应力

    公开(公告)号:US20120146054A1

    公开(公告)日:2012-06-14

    申请号:US13288170

    申请日:2011-11-03

    摘要: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

    摘要翻译: 集成电路仅包含源极侧的应力增强区域的晶体管。 在DeMOS晶体管中,仅在源极上形成应力增强区域并且在漏极延伸中不形成应力增强区域增加了漏极延伸区域的电阻,从而能够形成减小面积的DeMOS晶体管。 在MOS晶体管中,通过在源极侧形成应力增强区域,消除来自漏极侧的应力增强区域,降低了晶体管泄漏,提高了CHC可靠性。

    METHOD AND APPARATUS FOR PROCESSING IMAGE
    10.
    发明申请
    METHOD AND APPARATUS FOR PROCESSING IMAGE 有权
    用于处理图像的方法和装置

    公开(公告)号:US20110273594A1

    公开(公告)日:2011-11-10

    申请号:US13189058

    申请日:2011-07-22

    IPC分类号: H04N5/262 G06K9/32

    CPC分类号: G06T15/20 G06T3/0012

    摘要: A method for processing an image includes: obtaining depth values of an image including a target region and a non-target region; obtaining a scaling ratio of the target region; obtaining a scaling ratio of the non-target region according to the depth values of the image and the scaling ratio of the target region; scaling respectively the target region and the non-target region according to the scaling ratio of the target region and the scaling ratio of the non-target region, and obtaining a scaled image.

    摘要翻译: 一种处理图像的方法包括:获得包括目标区域和非目标区域的图像的深度值; 获得目标区域的缩放比例; 根据图像的深度值和目标区域的缩放比例获得非目标区域的缩放比例; 根据目标区域的缩放比率和非目标区域的缩放比例,分别对目标区域和非目标区域进行缩放,并获得缩放图像。