公开(公告)号：US07216310B2

公开(公告)日：2007-05-08

申请号：US10993815

申请日：2004-11-19

申请人： Amitava Chatterjee ,  David Barry Scott ,  Theodore W. Houston ,  Song Zhao ,  Shaoping Tang ,  Zhiqiang Wu

发明人： Amitava Chatterjee ,  David Barry Scott ,  Theodore W. Houston ,  Song Zhao ,  Shaoping Tang ,  Zhiqiang Wu

IPC分类号： G06F17/50 ,  G11C5/14 ,  H03K3/01 ,  G05F1/10

CPC分类号： G06F17/505

摘要： The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

摘要翻译： 本发明提供一种设计电路的方法（100）。 该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。 所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。 使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。 该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

公开(公告)号：US20120275207A1

公开(公告)日：2012-11-01

申请号：US13097370

申请日：2011-04-29

申请人： Theodore W. Houston ,  Puneet Kohli ,  Amitava Chatterjee

发明人： Theodore W. Houston ,  Puneet Kohli ,  Amitava Chatterjee

IPC分类号： G11C11/412 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/0207

摘要： An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.

摘要翻译： 具有SRAM单元的集成电路包括一对交叉耦合的反相器，其中第一驱动器和负载晶体管被连接以提供第一存储节点和第二驱动器以及连接到第二存储节点的负载晶体管。 SRAM单元还包括由至少一个字线控制并分别连接在第一位线和第一存储节点之间的第一和第二通过栅极晶体管以及第二位线和第二存储节点; 其中第一驱动晶体管阈值电压不同于第二驱动晶体管阈值电压，并且第一和第二驱动器阈值电压中的一个不同于通过栅极晶体管阈值电压。 或者，第一和第二驱动晶体管的阈值电压不同于对称的通过栅极晶体管阈值电压。 另外，提供了具有SRAM单元的集成电路的制造方法。

公开(公告)号：US09059032B2

公开(公告)日：2015-06-16

申请号：US13097370

申请日：2011-04-29

申请人： Theodore W. Houston ,  Puneet Kohli ,  Amitava Chatterjee

发明人： Theodore W. Houston ,  Puneet Kohli ,  Amitava Chatterjee

IPC分类号： G11C11/00 ,  H01L27/11 ,  H01L27/02 ,  G11C11/412

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/0207

摘要： An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.

摘要翻译： 具有SRAM单元的集成电路包括一对交叉耦合的反相器，其中第一驱动器和负载晶体管被连接以提供第一存储节点和第二驱动器以及连接到第二存储节点的负载晶体管。 SRAM单元还包括由至少一个字线控制并分别连接在第一位线和第一存储节点之间的第一和第二通过栅极晶体管以及第二位线和第二存储节点; 其中第一驱动晶体管阈值电压不同于第二驱动晶体管阈值电压，并且第一和第二驱动器阈值电压中的一个不同于通过栅极晶体管阈值电压。 或者，第一和第二驱动晶体管的阈值电压不同于对称的通过栅极晶体管阈值电压。 另外，提供了具有SRAM单元的集成电路的制造方法。

公开(公告)号：US06873008B2

公开(公告)日：2005-03-29

申请号：US10682729

申请日：2003-10-10

申请人： Theodore W. Houston ,  Amitava Chatterjee

发明人： Theodore W. Houston ,  Amitava Chatterjee

IPC分类号： H01L21/8234 ,  H01L29/76

CPC分类号： H01L21/823456 ,  H01L21/823425

摘要： An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of the channel region. One way to achieve this arrangement with disposable gate processing is to add disposable sidewalls inside the gate opening (after removing the disposable gate), patterning to selectively remove the source or gate side sidewalls, implant the source and drain regions and remove the remaining sidewall and the proceed. According to a second embodiment, wherein the channel implant can be symmetrical, a relatively low net VT implant is provided in the central region of the channel and a relatively high net VT implant is provided in the channel regions adjacent to the source and drain regions.

摘要翻译： 从源极到漏极的不对称沟道注入改善了短沟道特性。 植入物在源区域附近提供相对较高的VT净掺杂物，并且在沟道区域的其余部分中提供相对低的VT净掺杂剂。 通过一次性浇口处理实现这种布置的一种方式是在浇口开口内（在移除一次性浇口之后）添加一次性侧壁，图案化以选择性地移除源侧或侧壁侧壁，注入源区和漏区， 进行。 根据第二实施例，其中通道植入物可以是对称的，在通道的中心区域中提供相对较低的净VT植入物，并且在与源极和漏极区域相邻的沟道区域中提供相对较高的净VT注入。

公开(公告)号：US06548359B1

公开(公告)日：2003-04-15

申请号：US09368387

申请日：1999-08-04

申请人： Theodore W. Houston ,  Amitava Chatterjee

发明人： Theodore W. Houston ,  Amitava Chatterjee

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/823425

摘要： An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of the channel region. One way to achieve this arrangement with disposable gate processing is to add disposable sidewalls inside the gate opening (after removing the disposable gate), patterning to selectively remove the source or gate side sidewalls, implant the source and drain regions and remove the remaining sidewall and the proceed. According to a second embodiment, wherein the channel implant can be symmetrical, a relatively low net VT implant is provided in the central region of the channel and a relatively high net VT implant is provided in the channel regions adjacent to the source and drain regions.

公开(公告)号：US5909628A

公开(公告)日：1999-06-01

申请号：US804484

申请日：1997-02-21

申请人： Amitava Chatterjee ,  Theodore W. Houston ,  Ih-Chin Chen ,  Agerico L. Esquirel ,  Somnath Nag ,  Iqbal Ali ,  Keith A. Joyner ,  Yin Hu ,  Jeffrey Alan McKee ,  Peter Stewart McAnally

发明人： Amitava Chatterjee ,  Theodore W. Houston ,  Ih-Chin Chen ,  Agerico L. Esquirel ,  Somnath Nag ,  Iqbal Ali ,  Keith A. Joyner ,  Yin Hu ,  Jeffrey Alan McKee ,  Peter Stewart McAnally

IPC分类号： H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/78

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

摘要： A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

摘要翻译： 制造半导体器件或集成电路的技术产生平坦化的补充层，其在抛光之后具有比较均匀的厚度，例如通过化学机械抛光（CMP）。 在通常由场氧化物占据的衬底的该部分中的有源区域之间插入虚拟有源区，以便在这些区域中减少在CMP期间发生的“凹陷”。 虚拟有源区域可以采取大块，部分或完全形成的环形结构的形状，或者可以调节其面积密度以匹配衬底的该区域中的有源区的面积密度的多个柱。 支柱的设计规则可以是在多晶硅线或第一级金属化线被放置以避免寄生电容的地方放置柱子。

公开(公告)号：US07236396B2

公开(公告)日：2007-06-26

申请号：US11171033

申请日：2005-06-30

申请人： Theodore W. Houston ,  David Barry Scott ,  Sudha Thiruvengadam

发明人： Theodore W. Houston ,  David Barry Scott ,  Sudha Thiruvengadam

IPC分类号： G11C11/34

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104

摘要： An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure provides a continuous cell array at the lower cell patterning levels. The SRAM array includes a first and second array block each including an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells.

摘要翻译： 具有虚拟单元行结构的SRAM阵列，其中SRAM阵列被划分成由虚设单元的行图案隔离的段。 虚拟单元结构在较低单元图案化水平下提供连续的单元阵列。 SRAM阵列包括第一和第二阵列块，每个第一和第二阵列块包括具有第一布局配置的SRAM单元，一个或多个虚拟单元具有沿着与SRAM阵列的字线相关联的行图案布置的第二布局配置，第一功率 连接到第一阵列块的电源电压线和连接到第二阵列块的第二不同电源电压线。 阵列块的第一和第二电源电压线还连接到一个或多个虚设单元。

公开(公告)号：US09124263B2

公开(公告)日：2015-09-01

申请号：US13116973

申请日：2011-05-26

申请人： Theodore W. Houston ,  Andrew Marshall

发明人： Theodore W. Houston ,  Andrew Marshall

IPC分类号： G05F1/10 ,  G05F3/02 ,  H03K19/00 ,  H03K17/687

CPC分类号： H03K19/0016 ,  H03K17/687 ,  H03K2217/0018 ,  H03K2217/0036

摘要： A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor.

摘要翻译： 身体偏置协调器被提供用于使用体区的晶体管。 在一个示例中，主体偏置协调器包括被配置为控制晶体管并使其可操作以在激活晶体管期间从源电压提供虚拟电源电压的控制单元。 身体偏置协调器还包括耦合到控制单元并被配置为在晶体管的激活期间将身体区域连接到虚拟电源电压的连接单元。 在替代实施例中，连接单元还被配置为在晶体管的非激活期间将身体区域连接到另一电压。

公开(公告)号：US08891287B2

公开(公告)日：2014-11-18

申请号：US13196010

申请日：2011-08-02

申请人： Anand Seshadri ,  Theodore W. Houston

发明人： Anand Seshadri ,  Theodore W. Houston

IPC分类号： G11C11/40 ,  G11C11/412 ,  G11C11/419

CPC分类号： G11C11/412 ,  G11C11/419

摘要： A process of performing an SRAM single sided write operation including applying a positive bias increment to an isolated p-well containing a passgate in an addressed SRAM cell. A process of performing an SRAM single sided read operation including applying a negative bias increment to an isolated p-well containing a driver in an addressed SRAM cell. A process of performing an SRAM double sided write operation including applying a positive bias increment to an isolated p-well containing a passgate connected to a low data line in an addressed SRAM cell. A process of performing an SRAM double sided read operation including applying a negative bias increment to an isolated p-well containing a bit driver and applying a negative bias increment to an isolated p-well containing a bit-bar driver in an addressed SRAM cell.

摘要翻译： 一种执行SRAM单面写入操作的过程，包括在寻址的SRAM单元中对包含通孔的隔离p阱施加正偏置增量。 执行SRAM单面读取操作的过程包括对包含寻址的SRAM单元中的驱动器的隔离p阱施加负偏置增量。 执行SRAM双面写入操作的过程包括向包含连接到寻址的SRAM单元中的低数据线的通路的隔离p阱施加正偏置增量。 执行SRAM双面读取操作的过程包括向包含比特驱动器的隔离p阱施加负偏置增量，并且在寻址的SRAM单元中向包含位线驱动器的隔离p阱施加负偏置增量。

公开(公告)号：US08535990B2

公开(公告)日：2013-09-17

申请号：US12975006

申请日：2010-12-21

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： H01L21/82

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1207

摘要： An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation.