公开(公告)号：US20060014387A1

公开(公告)日：2006-01-19

申请号：US11155151

申请日：2005-06-17

Applicant: Lance Robertson ,  Jiong-Ping Lu ,  Donald Miles

Inventor： Lance Robertson ,  Jiong-Ping Lu ,  Donald Miles

IPC: H01L21/44

CPC classification number: H01L27/0629 ,  H01L21/28518 ,  H01L28/24 ,  H01L29/7833

Abstract: A silicide 160 is formed in exposed silicon on a semiconductor wafer 10 by a method that includes forming a thin interface layer 140 over the semiconductor wafer 10 and performing a first low temperature anneal to create the silicide 160. The method further includes removing an unreacted portion of the interface layer 140 and performing a second low temperature anneal to complete the formation of a low resistance silicide 160.

Abstract translation: 硅化物160通过包括在半导体晶片10上形成薄界面层140并进行第一低温退火以形成硅化物160的方法在半导体晶片10的暴露硅中形成。该方法还包括去除未反应部分 并执行第二低温退火以完成低电阻硅化物160的形成。

公开(公告)号：US20050208764A1

公开(公告)日：2005-09-22

申请号：US11073982

申请日：2005-03-07

Applicant: Jiong-Ping Lu ,  Duofeng Yue ,  Xiaozhan Liu ,  Donald Miles ,  Lance Robertson

Inventor： Jiong-Ping Lu ,  Duofeng Yue ,  Xiaozhan Liu ,  Donald Miles ,  Lance Robertson

IPC: H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/7833

Abstract: Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.

Abstract translation: 含氟区域（70）形成在MOS晶体管的源区和漏区（60）中。 在含氟区域（70）和源极和漏极区域（60）之上形成金属层（90）。 金属层与下面的含氟区域反应以形成金属硅化物。

公开(公告)号：US07422968B2

公开(公告)日：2008-09-09

申请号：US10901756

申请日：2004-07-29

Applicant: Jiong-Ping Lu ,  Clint Montgomery ,  Lindsey Hall ,  Donald Miles ,  Duofeng Yue ,  Thomas D. Bonifiield

Inventor： Jiong-Ping Lu ,  Clint Montgomery ,  Lindsey Hall ,  Donald Miles ,  Duofeng Yue ,  Thomas D. Bonifiield

IPC: H01L21/425

CPC classification number: H01L21/823835 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/02068 ,  H01L27/0629 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).

Abstract translation: 本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法。 除了其他步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（120）并且在栅极结构（120）附近的衬底（110）中形成源极/漏极区域（190） ）。 该方法还包括对栅极结构（120）和衬底（110）进行干蚀刻工艺，并且在将栅极结构（120）和衬底（120）经受栅极结构（120）和衬底 （110）到干蚀刻工艺。 此后，该方法包括在栅极结构（120）和氟化源极/漏极（320）中形成金属硅化物区域（510,520）。

公开(公告)号：US20050093034A1

公开(公告)日：2005-05-05

申请号：US10983257

申请日：2004-11-04

Applicant: Donald Miles

Inventor： Donald Miles

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of reducing dopant losses is provided. The method includes providing a transistor structure having a first region, implanting a dopant into the first region, depositing a control layer adjacent the first region, and performing a first annealing process on the transistor structure. The control layer is operable to prevent at least a portion of the dopant in the first region from diffusing out of the first region toward the control layer during the first annealing process.

Abstract translation: 提供了减少掺杂剂损失的方法。 该方法包括提供具有第一区域的晶体管结构，将掺杂剂注入第一区域，沉积与第一区域相邻的控制层，以及对晶体管结构执行第一退火处理。 控制层可操作以防止第一区域内的掺杂剂的至少一部分在第一退火过程期间从第一区域扩散到控制层。

公开(公告)号：US20050090087A1

公开(公告)日：2005-04-28

申请号：US10977433

申请日：2004-10-29

Applicant: Jiong-Ping Lu ,  Glenn Tessmer ,  Melissa Hewson ,  Donald Miles ,  Ralf Willecke ,  Andrew McKerrow ,  Brian Kirkpatrick ,  Clinton Montgomery

Inventor： Jiong-Ping Lu ,  Glenn Tessmer ,  Melissa Hewson ,  Donald Miles ,  Ralf Willecke ,  Andrew McKerrow ,  Brian Kirkpatrick ,  Clinton Montgomery

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L29/78 ,  H01L29/786 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/28052 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/321 ,  H01L21/3211 ,  H01L21/76834 ,  H01L29/665

Abstract: A process for forming nickel silicide and silicon nitride structure in a semiconductor integrated circuit device is described. Good adhesion between the nickel silicide and the silicon nitride is accomplished by passivating the nickel silicide surface with nitrogen. The passivation may be performed by treating the nickel silicide surface with plasma activated nitrogen species. An alternative passivation method is to cover the nickel silicide with a film of metal nitride and heat the substrate to about 500° C. Another alternative method is to sputter deposit silicon nitride on top of nickel silicide.

Abstract translation: 描述了在半导体集成电路器件中形成硅化镍和氮化硅结构的工艺。 通过用氮气钝化硅化镍表面，可以实现硅化镍和氮化硅之间的良好粘附。 可以通过用等离子体活化的氮物种处理硅化镍表面来进行钝化。 替代的钝化方法是用金属氮化物膜覆盖硅化镍，并将衬底加热至约500℃。另一种替代方法是在硅化镍顶部溅射沉积氮化硅。

公开(公告)号：US20090189444A1

公开(公告)日：2009-07-30

申请号：US12010466

申请日：2008-01-25

Applicant: Donald Miles Currie ,  Mark Edward Hartman ,  Benjamin Paul Gottemoller ,  Matthew Lee Boggs

Inventor： Donald Miles Currie ,  Mark Edward Hartman ,  Benjamin Paul Gottemoller ,  Matthew Lee Boggs

IPC: H02J1/10

CPC classification number: H02J1/10 ,  Y10T307/305

Abstract: A power supply system for supplying power to a load is disclosed. The power supply system includes a power source, a high voltage terminal coupled to the power source, a programmable controller coupled to the power source, and a first low voltage terminal and a second low voltage terminal. Each low voltage terminal is coupled to the programmable controller. The programmable controller may be programmed to switch each of the first and second low voltage terminals between a connected state and a disconnected state and to implement a power up strategy when initially supplying power to the load.

Abstract translation: 公开了一种向负载供电的电源系统。 电源系统包括电源，耦合到电源的高压端子，耦合到电源的可编程控制器以及第一低电压端子和第二低电压端子。 每个低电压端子耦合到可编程控制器。 可编程控制器可以被编程为在连接状态和断开状态之间切换第一和第二低压端子中的每一个，并且在最初向负载供电时实施上电策略。

公开(公告)号：US20060258091A1

公开(公告)日：2006-11-16

申请号：US11127669

申请日：2005-05-12

Applicant: Juanita DeLoach ,  Lindsey Hall ,  Lance Robertson ,  Jiong-Ping Lu ,  Donald Miles

Inventor： Juanita DeLoach ,  Lindsey Hall ,  Lance Robertson ,  Jiong-Ping Lu ,  Donald Miles

IPC: H01L21/336

CPC classification number: H01L21/28052 ,  H01L21/28518 ,  H01L29/665

Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).

Abstract translation: 本发明提供一种制造半导体器件的方法。 在本发明的一个实施例中，但不限于，用于制造半导体器件的方法包括在衬底（110）上形成栅极结构（120）并且在靠近栅极的衬底（110）中形成源/漏区（190） 结构（120）。 该方法还包括在源极/漏极区（190）中使用含氟等离子体，使用小于约75瓦特的功率电平形成含氟区域（220），在基底（110）上形成金属层（310），以及 含氟区域（220），并且使金属层（310）与含氟区域（220）反应以在源极/漏极区域（190）中形成金属硅化物区域（410）。

公开(公告)号：US20060024882A1

公开(公告)日：2006-02-02

申请号：US10901756

申请日：2004-07-29

Applicant: Jiong-Ping Lu ,  Clint Montgomery ,  Lindsey Hall ,  Donald Miles ,  Duofeng Yue ,  Thomas Bonifield

Inventor： Jiong-Ping Lu ,  Clint Montgomery ,  Lindsey Hall ,  Donald Miles ,  Duofeng Yue ,  Thomas Bonifield

IPC: H01L21/336

CPC classification number: H01L21/823835 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/02068 ,  H01L27/0629 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).

Abstract translation: 本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法。 除了其他步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（120）并且在栅极结构（120）附近的衬底（110）中形成源极/漏极区域（190） ）。 该方法还包括对栅极结构（120）和衬底（110）进行干蚀刻工艺，并且在将栅极结构（120）和衬底（120）经受栅极结构（120）和衬底 （110）到干蚀刻工艺。 此后，该方法包括在栅极结构（120）和氟化源极/漏极（320）中形成金属硅化物区域（510,520）。

公开(公告)号：US20060019478A1

公开(公告)日：2006-01-26

申请号：US10896599

申请日：2004-07-21

Applicant: Song Zhao ,  Sue Crank ,  Amitava Chatterjee ,  Kaiping Liu ,  Jiong-Ping Lu ,  Donald Miles ,  Duofeng Yue ,  Lance Robertson

Inventor： Song Zhao ,  Sue Crank ,  Amitava Chatterjee ,  Kaiping Liu ,  Jiong-Ping Lu ,  Donald Miles ,  Duofeng Yue ,  Lance Robertson

IPC: H01L21/28

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665

Abstract: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.