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    Column A/D converter, column A/D conversion method, solid imaging device, and camera system
    1.
    发明授权
    Column A/D converter, column A/D conversion method, solid imaging device, and camera system 有权
    列A / D转换器，列A / D转换方法，固体成像装置和相机系统

    公开(公告)号：US09357147B2

    公开(公告)日：2016-05-31

    申请号：US14375864

    申请日：2013-02-20

    Applicant: Sony Corporation

    Inventor： Yuusuke Nishida ,  Yasuaki Hisamatsu

    IPC: H04N5/335 ,  H04N5/3745 ,  H03K4/08 ,  H03K21/02 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H04N5/378 ,  H03M1/08 ,  H04N5/357 ,  H03M1/56

    CPC classification number: H04N5/37455 ,  H03K4/08 ,  H03K21/023 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/0624 ,  H03M1/0845 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/123 ,  H03M1/56 ,  H04N5/3577 ,  H04N5/378

    Abstract: The present invention relates to a column A/D converter, column A/D conversion method, imaging device, and camera system that can reduce the amount of IR drop by dispersing the current consumed during the count operation, mitigate the counter characteristic degradation, readily reduce the amount of fluctuation in the power source voltage, and achieve operation at a low power source voltage. The column A/D converter includes a plurality of column processing units including an A/D conversion function, a plurality of counters configured to generate digital codes in response to a reference clock and arranged corresponding to each or a set of the column processing units, and a count start offset unit configured to trigger a pseudo count operation in each of the counters and to offset a count start code for at least two or more counters among the plurality of counters before the reference clock is supplied to the counters.

    Abstract translation: 本发明涉及一种列A / D转换器，列A / D转换方法，成像装置和照相机系统，其可以通过分散在计数操作期间消耗的电流来减少IR降低量，从而容易地减轻反特性劣化 降低电源电压的波动量，实现低电源电压的动作。 列A / D转换器包括多个列处理单元，其包括A / D转换功能，多个计数器被配置为响应于参考时钟生成数字代码，并且对应于每个或一组列处理单元布置， 以及计数开始偏移单元，被配置为触发每个计数器中的伪计数操作，并且在将参考时钟提供给计数器之前偏移多个计数器中的至少两个或更多个计数器的计数开始代码。

    Solid state image sensor and electronic apparatus
    2.
    发明授权
    Solid state image sensor and electronic apparatus 有权

    公开(公告)号：US09930283B2

    公开(公告)日：2018-03-27

    申请号：US15502800

    申请日：2015-08-06

    Applicant: SONY CORPORATION

    Inventor： Takahiro Abiru ,  Yasuaki Hisamatsu ,  Tadafumi Nagata

    IPC: H03M1/56 ,  H04N5/378 ,  H03M1/82 ,  H03M1/66

    CPC classification number: H04N5/378 ,  H03M1/123 ,  H03M1/1295 ,  H03M1/56 ,  H03M1/66 ,  H03M1/82

    Abstract: The present disclosure relates to a solid state image sensor and an electronic apparatus capable of performing a gain transition at high speed. A ramp generation circuit includes sample hold circuits and ramp generation DACs, the number of which depends on kinds of required gains (for example, two kinds, i.e. a low gain and a high gain). Then, the two sample hold circuits can individually hold gain DAC output voltages at the different gains. This enables a switch to the ramp generation DAC holding the required gain voltage by means of a ramp selection signal. The present disclosure can be applied, for example, to a CMOS solid state image sensor that is used for an imaging device.

    Counter, counting method, ad converter, solid-state imaging device, and electronic device
    3.
    发明授权
    Counter, counting method, ad converter, solid-state imaging device, and electronic device 有权
    计数器，计数方法，广告转换器，固态成像设备和电子设备

    公开(公告)号：US09042508B2

    公开(公告)日：2015-05-26

    申请号：US13899711

    申请日：2013-05-22

    Applicant: Sony Corporation

    Inventor： Yasuaki Hisamatsu

    IPC: H03K23/00 ,  H03M1/34 ,  H03K23/86 ,  H03K21/02 ,  H03K21/38

    CPC classification number: H04N5/3742 ,  H03K21/023 ,  H03K21/026 ,  H03K21/38 ,  H03K23/86 ,  H03M1/34 ,  H04N5/37455 ,  H04N5/3765

    Abstract: A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

    Abstract translation: 配置为在输入时钟的两个边缘执行计数以输出先前计数值和下一个计数值的附加值或减法值的计数器包括锁存输入时钟的第一锁存电路，锁存输入时钟的第二锁存电路 从第一锁存电路输出的保持部，保持计数值的第0位的数据的校正部，以及基于计数值的输出对计数值的第1位和后续位的数据进行计数校正的校正部 第二锁存电路。

    COLUMN A/D CONVERTER, COLUMN A/D CONVERSION METHOD, SOLID IMAGING DEVICE, AND CAMERA SYSTEM
    6.
    发明申请
    COLUMN A/D CONVERTER, COLUMN A/D CONVERSION METHOD, SOLID IMAGING DEVICE, AND CAMERA SYSTEM 有权
    柱A / D转换器，柱A / D转换方法，固体成像装置和相机系统

    公开(公告)号：US20150326811A1

    公开(公告)日：2015-11-12

    申请号：US14375864

    申请日：2013-02-20

    Applicant: SONY CORPORATION

    Inventor： Yuusuke Nishida ,  Yasuaki Hisamatsu

    IPC: H04N5/3745 ,  H03K21/02 ,  H04N5/378 ,  H03M1/06 ,  H03M1/12 ,  H03K4/08 ,  H03M1/00

    CPC classification number: H04N5/37455 ,  H03K4/08 ,  H03K21/023 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/0624 ,  H03M1/0845 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/123 ,  H03M1/56 ,  H04N5/3577 ,  H04N5/378

    Abstract: The present invention relates to a column A/D converter, column A/D conversion method, imaging device, and camera system that can reduce the amount of IR drop by dispersing the current consumed during the count operation, mitigate the counter characteristic degradation, readily reduce the amount of fluctuation in the power source voltage, and achieve operation at a low power source voltage. The column A/D converter includes a plurality of column processing units including an A/D conversion function, a plurality of counters configured to generate digital codes in response to a reference clock and arranged corresponding to each or a set of the column processing units, and a count start offset unit configured to trigger a pseudo count operation in each of the counters and to offset a count start code for at least two or more counters among the plurality of counters before the reference clock is supplied to the counters.

    Abstract translation: 本发明涉及一种列A / D转换器，列A / D转换方法，成像装置和照相机系统，其可以通过分散在计数操作期间消耗的电流来减少IR降低量，从而容易地减轻反特性劣化 降低电源电压的波动量，实现低电源电压的动作。 列A / D转换器包括多个列处理单元，其包括A / D转换功能，多个计数器被配置为响应于参考时钟生成数字代码，并且对应于每个或一组列处理单元布置， 以及计数开始偏移单元，被配置为触发每个计数器中的伪计数操作，并且在将参考时钟提供给计数器之前偏移多个计数器中的至少两个或更多个计数器的计数开始代码。

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