公开(公告)号：US06670670B2

公开(公告)日：2003-12-30

申请号：US10125597

申请日：2002-04-19

申请人： Soo-doo Chae ,  Byong-man Kim ,  Moon-kyung Kim ,  Hee-soon Chae ,  Won-il Ryu

发明人： Soo-doo Chae ,  Byong-man Kim ,  Moon-kyung Kim ,  Hee-soon Chae ,  Won-il Ryu

IPC分类号： H01L29788

CPC分类号： B82Y10/00 ,  G11C2216/08 ,  H01L21/28273 ,  H01L29/7888

摘要： A single electron memory device including quantum dots between a gate electrode and a single electron storage element and a method for manufacturing the same, wherein the single electron memory device includes a substrate on which a nano-scale channel region is formed between a source and a drain, and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage medium storing a single electron tunneling through the lower layer formed on the lower layer, an upper layer including quantum dots formed on the single electron storage medium, and a gate electrode formed on the upper layer to be in contact with the quantum dots.

公开(公告)号：US06946346B2

公开(公告)日：2005-09-20

申请号：US10681346

申请日：2003-10-09

申请人： Soo-doo Chae ,  Byong-man Kim ,  Moon-kyung Kim ,  Hee-soon Chae ,  Won-il Ryu

发明人： Soo-doo Chae ,  Byong-man Kim ,  Moon-kyung Kim ,  Hee-soon Chae ,  Won-il Ryu

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： B82Y10/00 ,  G11C2216/08 ,  H01L21/28273 ,  H01L29/7888

摘要： In a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET, formation of the gate lamination pattern includes sequentially forming a lower layer and a single electron storage medium for storing a single electron tunneling through the lower layer on a substrate, forming an upper layer including a plurality of quantum dots on the single electron storage medium, forming a gate electrode layer on the upper layer to be in contact with the plurality of quantum dots, and patterning the lower layer, the single electron storage medium, the upper layer, and the gate electrode layer, in reverse order.

摘要翻译： 在形成在MOSFET的纳米尺度沟道区上的栅极层叠图案中包括单个电子存储元件的单电子存储器件的制造方法中，形成栅叠层图案包括顺序地形成下层和单电子存储 用于存储通过基底上的下层的单电子隧穿的介质，在单个电子存储介质上形成包括多个量子点的上层，在上层形成与多个量子相接触的栅电极层 点，并以相反的顺序图案化下层，单电子存储介质，上层和栅极电极层。

公开(公告)号：US20070138541A1

公开(公告)日：2007-06-21

申请号：US11702064

申请日：2007-02-05

申请人： Soo-doo Chae ,  Chung-woo Kim ,  Jo-won Lee ,  Moon-kyung Kim

发明人： Soo-doo Chae ,  Chung-woo Kim ,  Jo-won Lee ,  Moon-kyung Kim

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0466

摘要： A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.

摘要翻译： SONOS存储器件和从其中擦除数据的方法包括将第二符号的电荷载体注入陷阱膜，捕获膜俘获第一符号的电荷载体以在其中存储数据。 第二符号的电荷载体由形成在与至少一个位线接触的第一和第二电极中的一个与接触字线的栅电极之间的电场产生。 可以在栅电极和捕获膜之间设置阻挡膜。 第二标志的电荷载体可能是热孔。 这种擦除提高了擦除速度，从而提高了SONOS存储器件的性能。

公开(公告)号：US20090010058A1

公开(公告)日：2009-01-08

申请号：US12209735

申请日：2008-09-12

申请人： Soo-doo CHAE ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

发明人： Soo-doo CHAE ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.

摘要翻译： 可以提供多位非易失性存储器件及其操作和制造方法。 存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。 此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。 第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

公开(公告)号：US07187030B2

公开(公告)日：2007-03-06

申请号：US10867706

申请日：2004-06-16

申请人： Soo-doo Chae ,  Chung-woo Kim ,  Jo-won Lee ,  Moon-kyung Kim

发明人： Soo-doo Chae ,  Chung-woo Kim ,  Jo-won Lee ,  Moon-kyung Kim

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0466

摘要： A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.

摘要翻译： SONOS存储器件和从其中擦除数据的方法包括将第二符号的电荷载体注入陷阱膜，捕获膜俘获第一符号的电荷载体以在其中存储数据。 第二符号的电荷载体由形成在与至少一个位线接触的第一和第二电极中的一个与接触字线的栅电极之间的电场产生。 可以在栅电极和捕获膜之间设置阻挡膜。 第二标志的电荷载体可能是热孔。 这种擦除提高了擦除速度，从而提高了SONOS存储器件的性能。

公开(公告)号：US20090068808A1

公开(公告)日：2009-03-12

申请号：US12230423

申请日：2008-08-28

申请人： Soo-doo Chae ,  Chung-woo Kim ,  Jung-hyun Lee ,  Moon-kyung Kim ,  Hyun-sang Hwang

发明人： Soo-doo Chae ,  Chung-woo Kim ,  Jung-hyun Lee ,  Moon-kyung Kim ,  Hyun-sang Hwang

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28194 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si3N4); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.

摘要翻译： 非易失性半导体存储器件包括具有源极区和漏极区的半导体衬底，以及形成在半导体衬底上并与源极和漏极区接触的栅堆叠。 栅极堆叠从衬底依次顺序包括：隧道膜; 掺杂有第一预定杂质的第一捕获材料膜，所述第一捕获材料膜具有比所述氮化物膜（Si 3 N 4）更高的介电常数; 具有比氮化膜更高的介电常数的第一绝缘膜; 和栅电极。 这种非易失性半导体存储器件可以根据掺杂浓度有效地控制阱密度，从而在低工作电压下增加数据的写入/擦除速度。

公开(公告)号：US07420256B2

公开(公告)日：2008-09-02

申请号：US10835097

申请日：2004-04-30

申请人： Soo-doo Chae ,  Chung-woo Kim ,  Jung-hyun Lee ,  Moon-kyung Kim ,  Hyun-sang Hwang

发明人： Soo-doo Chae ,  Chung-woo Kim ,  Jung-hyun Lee ,  Moon-kyung Kim ,  Hyun-sang Hwang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28194 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si3N4); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.

摘要翻译： 非易失性半导体存储器件包括具有源极区和漏极区的半导体衬底，以及形成在半导体衬底上并与源极和漏极区接触的栅堆叠。 栅极堆叠从衬底依次顺序包括：隧道膜; 掺杂有第一预定杂质的第一捕获材料膜，所述第一捕获材料膜具有比所述氮化物膜（Si 3 N 4 N 4）更高的介电常数; 具有比氮化膜更高的介电常数的第一绝缘膜; 和栅电极。 这种非易失性半导体存储器件可以根据掺杂浓度有效地控制阱密度，从而在低工作电压下增加数据的写入/擦除速度。

公开(公告)号：US20050112815A1

公开(公告)日：2005-05-26

申请号：US10961481

申请日：2004-10-12

申请人： Moon-kyung Kim ,  Chung-woo Kim ,  Jo-won Lee ,  Eun-hong Lee ,  Hee-soon Chae

发明人： Moon-kyung Kim ,  Chung-woo Kim ,  Jo-won Lee ,  Eun-hong Lee ,  Hee-soon Chae

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.

摘要翻译： 在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造和操作方法中，SONOS存储器件包括包括源极和漏极区域以及沟道区域的半导体层，上部堆叠结构形成在 半导体层，上层堆叠结构和形成上SONOS存储器件的半导体层，以及形成在半导体层下的下堆叠结构，下堆叠结构和半导体层形成下SONOS存储器件。

公开(公告)号：US07759196B2

公开(公告)日：2010-07-20

申请号：US12209735

申请日：2008-09-12

申请人： Soo-doo Chae ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

发明人： Soo-doo Chae ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.

摘要翻译： 可以提供多位非易失性存储器件及其操作和制造方法。 存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。 此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。 第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

公开(公告)号：US20060108629A1

公开(公告)日：2006-05-25

申请号：US11220619

申请日：2005-09-08

申请人： Soo-doo Chae ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

发明人： Soo-doo Chae ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

IPC分类号： H01L29/788

CPC分类号： G11C16/0475 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7923

摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.

摘要翻译： 可以提供多位非易失性存储器件及其操作和制造方法。 存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。 此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。 第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。