公开(公告)号：US20060180853A1

公开(公告)日：2006-08-17

申请号：US11200153

申请日：2005-08-10

申请人： Won-il Ryu ,  Jo-won Lee ,  Se-wook Yoon ,  Chung-woo Kim

发明人： Won-il Ryu ,  Jo-won Lee ,  Se-wook Yoon ,  Chung-woo Kim

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.

摘要翻译： 在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造方法中，SONOS存储器件包括半导体衬底，沉积在半导体衬底上的绝缘层，形成在预定区域上的有源层 并且被分成源区域，漏极区域和沟道区域，形成在沟道区域的第一侧的第一侧栅叠层和形成在沟道区域的第二侧的第二侧栅叠层 与通道区域的第一侧相对。 在SONOS存储器件中，可以在每个SONOS存储器件中存储至少两位数据，从而允许半导体存储器件的集成密度增加而不增加其面积。

公开(公告)号：US06946346B2

公开(公告)日：2005-09-20

申请号：US10681346

申请日：2003-10-09

申请人： Soo-doo Chae ,  Byong-man Kim ,  Moon-kyung Kim ,  Hee-soon Chae ,  Won-il Ryu

发明人： Soo-doo Chae ,  Byong-man Kim ,  Moon-kyung Kim ,  Hee-soon Chae ,  Won-il Ryu

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： B82Y10/00 ,  G11C2216/08 ,  H01L21/28273 ,  H01L29/7888

摘要： In a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET, formation of the gate lamination pattern includes sequentially forming a lower layer and a single electron storage medium for storing a single electron tunneling through the lower layer on a substrate, forming an upper layer including a plurality of quantum dots on the single electron storage medium, forming a gate electrode layer on the upper layer to be in contact with the plurality of quantum dots, and patterning the lower layer, the single electron storage medium, the upper layer, and the gate electrode layer, in reverse order.

摘要翻译： 在形成在MOSFET的纳米尺度沟道区上的栅极层叠图案中包括单个电子存储元件的单电子存储器件的制造方法中，形成栅叠层图案包括顺序地形成下层和单电子存储 用于存储通过基底上的下层的单电子隧穿的介质，在单个电子存储介质上形成包括多个量子点的上层，在上层形成与多个量子相接触的栅电极层 点，并以相反的顺序图案化下层，单电子存储介质，上层和栅极电极层。

公开(公告)号：US06936884B2

公开(公告)日：2005-08-30

申请号：US10682984

申请日：2003-10-14

申请人： Soo-doo Chae ,  Ju-hyung Kim ,  Chung-woo Kim ,  Hee-soon Chae ,  Won-il Ryu

发明人： Soo-doo Chae ,  Ju-hyung Kim ,  Chung-woo Kim ,  Hee-soon Chae ,  Won-il Ryu

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28194 ,  B82Y10/00 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/7888

摘要： A nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) structure memory device includes a first insulating layer and a second insulating layer stacked on a channel of a substrate, a first dielectric layer and a second dielectric layer formed on the first insulating layer and under the second insulating layer, respectively, and a group IV semiconductor layer, silicon quantum dots, or metal quantum dots interposed between the first dielectric layer and the second dielectric layer. The provided SONSNOS structure memory device improves a programming rate and the capacity of the memory.

摘要翻译： 非易失性硅/氧化物/氮化物/氮/氮化物/氧化物/硅（SONSNOS）结构存储器件包括堆叠在衬底的沟道上的第一绝缘层和第二绝缘层，形成在衬底上的第一电介质层和第二电介质层 第一绝缘层和第二绝缘层下面的第一绝缘层，以及介于第一介电层和第二介电层之间的IV族半导体层，硅量子点或金属量子点。 所提供的SONSNOS结构存储器件提高了编程速率和存储器的容量。

公开(公告)号：US06664123B2

公开(公告)日：2003-12-16

申请号：US10029814

申请日：2001-12-28

申请人： Byong-man Kim ,  Soo-doo Chae ,  Hee-soon Chae ,  Won-il Ryu

发明人： Byong-man Kim ,  Soo-doo Chae ,  Hee-soon Chae ,  Won-il Ryu

IPC分类号： H01L2100

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  C23F4/00 ,  G11B9/10 ,  G11B9/14 ,  G11B9/1463 ,  G11B9/149 ,  H01J2237/31747

摘要： A method for etching a metal layer on a scale of nano meters, includes preparing a substrate on which a metal layer is formed, positioning a micro tip over the metal layer, generating an electron beam from the micro tip by applying a predetermined voltage between the metal layer and the micro tip, and etching the surface of the metal layer into a predetermined pattern with the electron beam. Accordingly, it is possible to form an etched pattern by applying a negative bias to a micro tip without applying a strong mechanical force to the micro tip, and heating/melting the metal layer with the use of an electron beam emitted from the micro tip which is negative-biased.

公开(公告)号：US06429472B2

公开(公告)日：2002-08-06

申请号：US09801731

申请日：2001-03-09

申请人： Byung-ki Kim ,  Won-il Ryu

发明人： Byung-ki Kim ,  Won-il Ryu

IPC分类号： H01L2972

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A split gate type flash memory having an active region that improves an endurance characteristic along with program/erase efficiency, wherein the split gate type flash memory provides for improvement in the endurance characteristic and program/erase efficiency by making the width of an active region in a portion in which a source is overlapped by a floating gate as large as possible.

摘要翻译： 一种具有有效区域的分裂门型闪速存储器，其具有改善耐久性特性以及编程/擦除效率的功能，其中分离栅型闪速存储器通过使有源区域的宽度成为可能性来提高耐久特性和编程/擦除效率 源极与浮动栅极重叠的部分尽可能大。

公开(公告)号：US20060134531A1

公开(公告)日：2006-06-22

申请号：US11274474

申请日：2005-11-16

申请人： I-Hun Song ,  Won-Il Ryu ,  Suk-Pil Kim ,  Hoon Kim ,  Seung-Hyuk Chang ,  Won-Joo Kim ,  Young-Soo Park

发明人： I-Hun Song ,  Won-Il Ryu ,  Suk-Pil Kim ,  Hoon Kim ,  Seung-Hyuk Chang ,  Won-Joo Kim ,  Young-Soo Park

IPC分类号： G03C5/00 ,  G21K5/00 ,  G03F1/00

CPC分类号： G21K1/062 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/24

摘要： A mask for lithography and a method of manufacturing the same. The mask may include a substrate, a reflection layer formed of a material capable of reflecting electromagnetic rays on the substrate and an absorption pattern formed in a desired pattern such that absorbing regions with respect to electromagnetic rays and windows through which electromagnetic rays pass are formed, wherein the absorption pattern includes at least one side surface that is adjacent to the window and is inclined with respect to the reflection layer. The method may include forming a reflection layer which is formed of a material capable of reflecting electromagnetic rays on a substrate, forming an absorption layer which is formed of a material capable of absorbing electromagnetic rays on the refection layer, and patterning the absorption layer to form an absorption pattern with at least one side surface adjacent to a window that has an inclined side surface with respect to the reflection layer.

摘要翻译： 光刻用掩模及其制造方法。 掩模可以包括基板，由能够在基板上反射电磁射线的材料形成的反射层和形成为期望图案的吸收图案，使得形成相对于电磁射线通过的电磁射线和窗口的吸收区域， 其中所述吸收图案包括与所述窗口相邻并且相对于所述反射层倾斜的至少一个侧表面。 该方法可以包括形成由能够在基板上反射电磁射线的材料形成的反射层，形成由能够在反射层上吸收电磁射线的材料形成的吸收层，以及图案化吸收层以形成 具有与窗口相邻的至少一个侧表面的吸收图案，该窗口具有相对于反射层的倾斜侧表面。

公开(公告)号：US06946703B2

公开(公告)日：2005-09-20

申请号：US10753772

申请日：2004-01-09

申请人： Won-il Ryu ,  Jo-won Lee ,  Se-wook Yoon ,  Chung-woo Kim

发明人： Won-il Ryu ,  Jo-won Lee ,  Se-wook Yoon ,  Chung-woo Kim

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.

摘要翻译： 在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造方法中，SONOS存储器件包括半导体衬底，沉积在半导体衬底上的绝缘层，形成在预定区域上的有源层 并且被分成源区域，漏极区域和沟道区域，形成在沟道区域的第一侧的第一侧栅叠层和形成在沟道区域的第二侧的第二侧栅叠层 与通道区域的第一侧相对。 在SONOS存储器件中，可以在每个SONOS存储器件中存储至少两位数据，从而允许半导体存储器件的集成密度增加而不增加其面积。

公开(公告)号：US07374991B2

公开(公告)日：2008-05-20

申请号：US11200153

申请日：2005-08-10

申请人： Won-il Ryu ,  Jo-won Lee ,  Se-wook Yoon ,  Chung-woo Kim

发明人： Won-il Ryu ,  Jo-won Lee ,  Se-wook Yoon ,  Chung-woo Kim

IPC分类号： H01L21/8238

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.

摘要翻译： 在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造方法中，SONOS存储器件包括半导体衬底，沉积在半导体衬底上的绝缘层，形成在预定区域上的有源层 并且被分成源区域，漏极区域和沟道区域，形成在沟道区域的第一侧的第一侧栅叠层和形成在沟道区域的第二侧的第二侧栅叠层 与通道区域的第一侧相对。 在SONOS存储器件中，可以在每个SONOS存储器件中存储至少两位数据，从而允许半导体存储器件的集成密度增加而不增加其面积。

公开(公告)号：US20060257753A1

公开(公告)日：2006-11-16

申请号：US11356258

申请日：2006-02-17

申请人： Won-joo Kim ,  I-hun Song ,  Suk-pil Kim ,  Seung-hyuk Chang ,  Won-Il Ryu ,  Hoon Kim

发明人： Won-joo Kim ,  I-hun Song ,  Suk-pil Kim ,  Seung-hyuk Chang ,  Won-Il Ryu ,  Hoon Kim

IPC分类号： G03C5/00 ,  G21K5/00 ,  G03F1/00

CPC分类号： G21K1/062 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/24 ,  G21K2201/067

摘要： A photomask and method thereof. In an example method, a photomask may be manufactured by forming an oxide layer on a surface, patterning the oxide layer to form an oxide pattern, the oxide pattern including a plurality of oxide pattern bodies and a plurality of oxide windows, filling the plurality of oxide windows with an absorbent to form an absorbent pattern and reducing the plurality of oxide pattern bodies. An example photomask may include an oxide pattern-based absorbent pattern including a plurality of absorbent pattern bodies and a plurality of absorbent pattern windows.

摘要翻译： 光掩模及其方法。 在一个示例性方法中，可以通过在表面上形成氧化物层来形成光掩模，图案化氧化物层以形成氧化物图案，氧化物图案包括多个氧化物图案体和多个氧化物窗口， 具有吸收剂的氧化物窗口以形成吸收图案并且还原多个氧化物图案体。 示例性光掩模可以包括基于氧化物图案的吸收图案，其包括多个吸收图案体和多个吸收图案窗。

公开(公告)号：US20050202639A1

公开(公告)日：2005-09-15

申请号：US11071192

申请日：2005-03-04

申请人： In-kyeong Yoo ,  Soo-hwan Jeong ,  Won-il Ryu

发明人： In-kyeong Yoo ,  Soo-hwan Jeong ,  Won-il Ryu

IPC分类号： H01L27/10 ,  H01L21/28 ,  H01L21/335 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/7883

摘要： Provided is a method of manufacturing a memory device that comprises a gate including uniformly distributed silicon nano dots. The method includes forming a gate on a substrate, the gate including, stacked in sequence an insulating film, nano dot layers separated by a predetermined lateral distance, and a conductive film pattern, forming a source region and a drain region contacting the gate in the substrate, and forming first and second metal layers on the source region and the drain region, respectively.

摘要翻译： 提供一种制造包括均匀分布的硅纳米点的栅极的存储器件的方法。 该方法包括在衬底上形成栅极，栅极包括依次层叠绝缘膜，以预定横向距离分隔的纳米点层和导电膜图案，形成与栅极接触的源极区域和漏极区域 并且分别在源极区域和漏极区域上形成第一和第二金属层。