Method and apparatus for programmable coupling between CPU and co-processor
    2.
    发明授权
    Method and apparatus for programmable coupling between CPU and co-processor 有权
    CPU与协处理器之间可编程耦合的方法和装置

    公开(公告)号:US08359462B1

    公开(公告)日:2013-01-22

    申请号:US12275981

    申请日:2008-11-21

    IPC分类号: G06F9/00 G06F9/30

    摘要: In one embodiment the present invention includes a method and apparatus for enabling a main core and one or more co-processors to operate in a de-coupled mode, thereby facilitating the execution of two or more instruction threads in parallel. A co-processor, according to an embodiment of the invention, has a coupling manager including a loop buffer for storing instructions which can be independently fetched and executed by the co-processor when operating in de-coupled mode. In addition, the coupling manager includes a loop descriptor and a counter/condition descriptor. The loop descriptor and condition descriptor work in conjunction with one another to determine what, if any, action should be taken when a co-processor is in a particular processing state, for example, as indicated by a counter keeping track of loop processing.

    摘要翻译: 在一个实施例中,本发明包括用于使主核和一个或多个协处理器能够以解耦合模式工作的方法和装置,从而有助于并行执行两个或更多个指令线程。 根据本发明的实施例的协处理器具有耦合管理器,其包括循环缓冲器,用于存储当以解耦模式操作时可由协处理器独立地取出并执行的指令。 另外,耦合管理器包括循环描述符和计数器/条件描述符。 循环描述符和条件描述符彼此协同工作,以确定当协处理器处于特定处理状态时应当采取什么(如果有的话),如由计数器跟踪循环处理所示。

    Method and apparatus for a trust processor
    3.
    发明授权
    Method and apparatus for a trust processor 有权
    信任处理器的方法和装置

    公开(公告)号:US08751818B2

    公开(公告)日:2014-06-10

    申请号:US12357245

    申请日:2009-01-21

    IPC分类号: G06F11/30 G06F12/14

    摘要: In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.

    摘要翻译: 在一个实施例中,一种装置包括无线装置内的密码处理器。 密码处理器包括至少一个加密单元。 密码处理器还包括用于存储一个或多个微代码指令的非易失性存储器,其中所述一个或多个微代码指令中的至少一个与敏感操作相关。 密码处理器还包括控制器,用于控制由至少一个密码单元执行一个或多个微代码指令,其中如果该设备处于不可信状态,则控制器将阻止执行敏感操作。

    System and method for peripheral device communications
    4.
    发明授权
    System and method for peripheral device communications 有权
    用于外围设备通信的系统和方法

    公开(公告)号:US08386666B2

    公开(公告)日:2013-02-26

    申请号:US13406007

    申请日:2012-02-27

    IPC分类号: G06F13/28 G06F13/24

    CPC分类号: G06F13/28

    摘要: A method for operating a host device includes comparing a predetermined response of a peripheral device to a response token received from the peripheral device. The predetermined response and the response token are generated based on a first command transmitted from the host device to the peripheral device. The method further includes controlling a transfer of first data from a first memory to a peripheral control module based on the comparison between the predetermined response and the response token without interrupting a host control module, and selectively passing interrupts to the host control module when the predetermined response does not match the response token.

    摘要翻译: 用于操作主机设备的方法包括将外围设备的预定响应与从外围设备接收的响应令牌进行比较。 基于从主机设备向外围设备发送的第一命令来生成预定响应和响应令牌。 该方法还包括基于预定响应和响应令牌之间的比较来控制从第一存储器到外围控制模块的传输,而不中断主机控制模块,以及当预定的时间间隔时间选择性地将中断传送到主机控制模块 响应与响应令牌不匹配。

    MEMORY POWER MANAGER
    5.
    发明申请
    MEMORY POWER MANAGER 有权
    内存电源管理器

    公开(公告)号:US20110276817A1

    公开(公告)日:2011-11-10

    申请号:US12774479

    申请日:2010-05-05

    IPC分类号: G06F1/32 G06F12/00 G06F1/00

    摘要: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

    摘要翻译: 控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。 基于时钟脉冲调整分配的时间值,并且生成优先权访问列表。 考虑的因素包括错过访问期限,接近缺少访问截止日期以及页面是否打开。 然后将最高排名的客户端传递给定序器以允许请求的访问。 时间值可以根据客户端ID或客户端类型(延迟或带宽)进行分配和调整。 定义了多个功率工作模式,其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。 处理通过相关的逻辑电路并行(同时)在硬件中执行。

    Method for supporting multiple devices on a high speed physical link
    7.
    发明授权
    Method for supporting multiple devices on a high speed physical link 失效
    用于在高速物理链路上支持多个设备的方法

    公开(公告)号:US07668190B1

    公开(公告)日:2010-02-23

    申请号:US10749942

    申请日:2003-12-31

    IPC分类号: H04J3/17

    CPC分类号: G06F13/4226 G06F13/36

    摘要: In some embodiments, a method for supporting multiple devices on a high speed physical link may be described. An embedded device may assert a link request pin to request to transmit data on a multi-point communications link that may serve a plurality of embedded devices. A controlling device may receive the link request signal. When the controlling device finishes sending data on the link, it may address the plurality of embedded devices in a round robin format and may determine which device asserted the link request pin. The embedded device that asserted the link request pin may send an acknowledgement signal to the controlling device when it is addressed.

    摘要翻译: 在一些实施例中,可以描述用于支持高速物理链路上的多个设备的方法。 嵌入式设备可以断言链路请求引脚以请求在可以服务于多个嵌入式设备的多点通信链路上传输数据。 控制装置可以接收链路请求信号。 当控制装置在链路上完成发送数据时,它可以以循环格式对多个嵌入式设备进行寻址,并且可以确定哪个设备断言了链路请求引脚。 断言链接请求引脚的嵌入式设备在寻址时可以向控制设备发送确认信号。

    METHOD AND APPARATUS FOR A TRUST PROCESSOR
    8.
    发明申请
    METHOD AND APPARATUS FOR A TRUST PROCESSOR 有权
    信托处理器的方法和装置

    公开(公告)号:US20090282263A1

    公开(公告)日:2009-11-12

    申请号:US12357245

    申请日:2009-01-21

    IPC分类号: H04L9/00

    摘要: In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.

    摘要翻译: 在一个实施例中,一种装置包括无线装置内的密码处理器。 密码处理器包括至少一个加密单元。 密码处理器还包括用于存储一个或多个微代码指令的非易失性存储器,其中所述一个或多个微代码指令中的至少一个与敏感操作相关。 密码处理器还包括控制器,用于控制由至少一个密码单元执行一个或多个微代码指令,其中如果该设备处于不可信状态,则控制器将阻止执行敏感操作。

    Streaming data engine
    9.
    发明授权
    Streaming data engine 有权
    流数据引擎

    公开(公告)号:US08135853B1

    公开(公告)日:2012-03-13

    申请号:US12270482

    申请日:2008-11-13

    IPC分类号: G06F15/16

    摘要: In one or more embodiments, a method, computer-readable media, system and or modules are capable of generating an address for a multimedia data block included in a stream of multimedia data. The address can be maintained in one or more local registers. The one or more local registers can be linked to one or more processor registers associated with a processor to synchronize communication of the stream of multimedia data with the processor.

    摘要翻译: 在一个或多个实施例中,方法,计算机可读介质,系统和/或模块能够为包含在多媒体数据流中的多媒体数据块生成地址。 地址可以保存在一个或多个本地寄存器中。 一个或多个本地寄存器可以链接到与处理器相关联的一个或多个处理器寄存器,以同步多媒体数据流与处理器的通信。

    Instruction pointers in very long instruction words
    10.
    发明授权
    Instruction pointers in very long instruction words 有权
    指令指针在很长的指令字中

    公开(公告)号:US08095775B1

    公开(公告)日:2012-01-10

    申请号:US12274235

    申请日:2008-11-19

    IPC分类号: G06F15/76 G06F9/38

    摘要: During operation of a VLIW processor, a very long instruction word is fetched. A portion of the very long instruction word that includes a pointer to an instruction is identified, and the instruction pointed to by the pointer is retrieved from a location of an instruction window. The retrieved instruction is input into a functional unit for execution.

    摘要翻译: 在VLIW处理器的操作期间,取出非常长的指令字。 识别包括指向指令的指针的长指令字的一部分,并且从指令窗口的位置检索指针指向的指令。 检索到的指令被输入到功能单元中以供执行。