公开(公告)号：US20080261395A1

公开(公告)日：2008-10-23

申请号：US11738086

申请日：2007-04-20

申请人： Stefan Blawid ,  Ludovic Lattard ,  Roman Knoefler ,  Manuela Gutsch ,  David Pritchard ,  Martin Roessiger

发明人： Stefan Blawid ,  Ludovic Lattard ,  Roman Knoefler ,  Manuela Gutsch ,  David Pritchard ,  Martin Roessiger

IPC分类号： H01L23/48 ,  G03F1/00 ,  H01L21/44

CPC分类号： H01L27/0203 ,  H01L27/105 ,  H01L27/115

摘要： Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned at an angle to the first structure, and the plurality of pad structures are intersecting at least one of the linear structures in the first structure. An electronic device with at least one semiconductor device, methods for manufacturing a semiconductor device and a mask system are also covered.

摘要翻译： 具有第一结构的半导体器件包括多个至少部分平行的线性结构，第二结构包括多个衬垫结构，至少部分地形成一组直线结构，弯曲结构，分段线性结构和分段弯曲 结构，其与第一结构成角度定位，并且多个垫结构在第一结构中与至少一个线性结构相交。 还包括具有至少一个半导体器件的电子器件，用于制造半导体器件的方法和掩模系统。

公开(公告)号：US08018070B2

公开(公告)日：2011-09-13

申请号：US11738086

申请日：2007-04-20

申请人： Stefan Blawid ,  Ludovic Lattard ,  Roman Knoefler ,  Manuela Gutsch ,  David Pritchard ,  Martin Roessiger

发明人： Stefan Blawid ,  Ludovic Lattard ,  Roman Knoefler ,  Manuela Gutsch ,  David Pritchard ,  Martin Roessiger

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/0203 ,  H01L27/105 ,  H01L27/115

摘要： Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned at an angle to the first structure, and the plurality of pad structures are intersecting at least one of the linear structures in the first structure. An electronic device with at least one semiconductor device, methods for manufacturing a semiconductor device and a mask system are also covered.

摘要翻译： 具有第一结构的半导体器件包括多个至少部分平行的线性结构，第二结构包括多个衬垫结构，至少部分地形成一组直线结构，弯曲结构，分段线性结构和分段弯曲 结构，其与第一结构成角度定位，并且多个垫结构在第一结构中与至少一个线性结构相交。 还包括具有至少一个半导体器件的电子器件，用于制造半导体器件的方法和掩模系统。

公开(公告)号：US20070243707A1

公开(公告)日：2007-10-18

申请号：US11686501

申请日：2007-03-15

申请人： Dirk Manger ,  Hocine Boubekeur ,  Martin Verhoeven ,  Nicolas Nagel ,  Thomas Tatry ,  Dirk Caspary ,  Matthias Markert ,  Lothar Bauch ,  Stefan Blawid ,  Manuela Gutsch ,  Ludovic Lattard ,  Martin Roessiger ,  Mirko Vogt

发明人： Dirk Manger ,  Hocine Boubekeur ,  Martin Verhoeven ,  Nicolas Nagel ,  Thomas Tatry ,  Dirk Caspary ,  Matthias Markert ,  Lothar Bauch ,  Stefan Blawid ,  Manuela Gutsch ,  Ludovic Lattard ,  Martin Roessiger ,  Mirko Vogt

IPC分类号： H01L21/44 ,  G03F1/00 ,  H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L27/105 ,  H01L27/112

摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

摘要翻译： 用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料 碳层顶部和设置在第一层顶部的硅层。 图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

公开(公告)号：US20070218627A1

公开(公告)日：2007-09-20

申请号：US11375912

申请日：2006-03-15

申请人： Ludovic Lattard ,  Martin Roessiger ,  Lothar Bauch ,  Stefan Blawid ,  Manuela Gutsch

发明人： Ludovic Lattard ,  Martin Roessiger ,  Lothar Bauch ,  Stefan Blawid ,  Manuela Gutsch

IPC分类号： H01L21/8242

CPC分类号： H01L27/0203 ,  H01L27/1052 ,  H01L27/10891

摘要： A method of forming a semiconductor device includes patterning a layer stack to form single conductive lines and single landing pads. Patterning of the layer stack includes two lithographic exposures using a set of two different photomasks. The landing pads are arranged at on side of an array region defined by a plurality of conductive lines. A set of photomasks used in the method of forming a semiconductor device includes a first photomask including patterns corresponding to the conductive lines and a second photomask including patterns corresponding to the landing pads. A semiconductor device includes conductive lines and landing pads connected with corresponding ones of said conductive lines wherein the landing pads are arranged in a staggered fashion at one side of an array region defined by a plurality of conductive lines.

摘要翻译： 形成半导体器件的方法包括图案化层叠以形成单个导电线和单个着陆焊盘。 层叠层的图案化包括使用一组两个不同光掩模的两次光刻曝光。 着陆焊盘布置在由多条导线限定的阵列区域的一侧。 在形成半导体器件的方法中使用的一组光掩模包括包括对应于导电线的图案的第一光掩模和包括对应于着陆焊盘的图案的第二光掩模。 半导体器件包括与对应的导电线连接的导电线和着陆焊盘，其中着陆焊盘以交错方式布置在由多条导线限定的阵列区域的一侧。

公开(公告)号：US20140175713A1

公开(公告)日：2014-06-26

申请号：US14238565

申请日：2012-07-31

申请人： Martin Roessiger ,  Günther Winter

发明人： Martin Roessiger ,  Günther Winter

IPC分类号： C21D9/00 ,  C21D11/00

CPC分类号： C21D9/0006 ,  C21D8/0447 ,  C21D8/0473 ,  C21D9/56 ,  C21D11/00 ,  G05B13/04 ,  H05B6/104 ,  Y02P10/253

摘要： A method operates a continuous annealing line for the processing of a rolled good, in particular a metal strip. A property of the rolled good in relation to a point or a section of the rolled good is fed to a computer-aided model as an input variable. The point or the section of the rolled good is located before or in the continuous annealing line. For the purpose of precise control of the continuous annealing process, at least one material property of the rolled good after the continuous annealing process is simulated by the computer-aided model and compared with a specified target value. If the simulated material property deviates from the target value, at least one process variable of the continuous annealing process is controlled as long as the point or the section of the rolled good is located before or in the continuous annealing line.

摘要翻译： 一种方法操作用于加工轧制品，特别是金属带的连续退火线。 与轧制品的点或部分相关的卷材的属性被馈送到作为输入变量的计算机辅助模型。 轧制件的点或部分位于连续退火线之前或之中。 为了精确控制连续退火工艺，通过计算机辅助模型模拟连续退火工艺后的轧制材料的至少一种材料性能，并与指定的目标值进行比较。 如果模拟材料性质偏离目标值，只要轧制品的点或部分位于连续退火线之前或之中，则控制连续退火工艺的至少一个工艺变量。

公开(公告)号：US20080296778A1

公开(公告)日：2008-12-04

申请号：US11755483

申请日：2007-05-30

申请人： Martin Roessiger ,  Christoph Kleint

发明人： Martin Roessiger ,  Christoph Kleint

IPC分类号： H01L23/52 ,  H01L21/3205

CPC分类号： H01L23/485 ,  H01L21/76837 ,  H01L21/76885 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing an integrated circuit and an interconnection structure includes forming a conductive portion along a first direction and conductive lines along a second direction.

摘要翻译： 集成电路和互连结构的制造方法包括沿着第一方向形成导电部分，沿着第二方向形成导电线。

公开(公告)号：US07177788B2

公开(公告)日：2007-02-13

申请号：US10272848

申请日：2002-10-17

申请人： Martin Roessiger

发明人： Martin Roessiger

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  G06F17/18

摘要： Input parameters and technically possible parameter values associated therewith are selected, from which are obtained support point values and result values assigned thereto for the geometrical properties. At each support point value, the respective result value is assigned to the parameter value assigned to the respective support point value. A response surface is adapted to the result values in a total range of the assigned parameter values. This results in response values for which a minimum value and a maximum value are determined in subranges. A total interval is formed from the largest response value overall and the smallest response value overall. The total interval is divided into a given number of sub-intervals. For each of the sub-intervals, the individual probabilities are cumulated, which yields a total probability value for a respective sub-interval over all the value intervals.

摘要翻译： 选择与其相关联的输入参数和技术上可能的参数值，从中获得支持点值和为其几何特性分配的结果值。 在每个支持点值处，将相应的结果值分配给分配给相应支持点值的参数值。 响应面适应于所分配的参数值的总范围内的结果值。 这导致在子范围内确定最小值和最大值的响应值。 总的时间间隔从整体最大响应值和最小响应值形成。 总间隔被分为给定数量的子间隔。 对于每个子间隔，单个概率被累积，其产生在所有值间隔上的相应子间隔的总概率值。

公开(公告)号：US20070264760A1

公开(公告)日：2007-11-15

申请号：US11433769

申请日：2006-05-15

申请人： Martin Roessiger

发明人： Martin Roessiger

IPC分类号： H01L21/8232

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A semiconductor substrate is provided. A plurality of first conductive lines is formed, followed by forming a plurality of second conductive lines above the first conductive lines. Memory cells are at least partially formed in the semiconductor substrate. Thereafter, at least one of the second conductive lines is removed, thereby forming an opened portion. A sacrificial material is filled into the opened portion and a first hardmask layer is provided. The first hardmask layer is patterned so as to form a pattern comprising lines and spaces, so that portions of the sacrificial material are uncovered. Thereafter, the uncovered portions of the sacrificial material are selectively etched, thereby forming contact openings. Finally, a conductive material is filled into the contact openings and a plurality of third conductive lines connected with the contact openings is provided.

摘要翻译： 提供半导体衬底。 形成多个第一导电线，随后在第一导线之上形成多个第二导线。 存储单元至少部分地形成在半导体衬底中。 此后，除去至少一个第二导线，从而形成开口部。 将牺牲材料填充到打开的部分中，并且提供第一硬掩模层。 图案化第一硬掩模层以形成包括线和间隔的图案，使得牺牲材料的部分未被覆盖。 此后，牺牲材料的未覆盖部分被选择性地蚀刻，从而形成接触开口。 最后，将导电材料填充到接触开口中，并且提供与接触开口连接的多个第三导线。