公开(公告)号：US20080028359A1

公开(公告)日：2008-01-31

申请号：US11496279

申请日：2006-07-31

Applicant: Stefan Blawid ,  Wolfram Koestler ,  Ralf Ziebold

Inventor： Stefan Blawid ,  Wolfram Koestler ,  Ralf Ziebold

IPC: G06F17/50

CPC classification number: H01L27/0203 ,  G03F1/00

Abstract: Termination structure for a pattern, especially an at least partially regular spaced pattern used in the manufacturing of semiconductor devices, especially DRAM-chips, wherein the termination structure comprises at least a first line-shaped element and at least one extension element adjacent to the first line-shaped element partially increasing the width of the first line-shaped element.

Abstract translation: 用于图案的端接结构，特别是用于制造半导体器件，特别是DRAM芯片的至少部分规则间隔的图案，其中终端结构包括至少第一线状元件和至少一个与第一线形元件相邻的延伸元件 线状元件部分地增加第一线状元件的宽度。

公开(公告)号：US20070243707A1

公开(公告)日：2007-10-18

申请号：US11686501

申请日：2007-03-15

Applicant: Dirk Manger ,  Hocine Boubekeur ,  Martin Verhoeven ,  Nicolas Nagel ,  Thomas Tatry ,  Dirk Caspary ,  Matthias Markert ,  Lothar Bauch ,  Stefan Blawid ,  Manuela Gutsch ,  Ludovic Lattard ,  Martin Roessiger ,  Mirko Vogt

Inventor： Dirk Manger ,  Hocine Boubekeur ,  Martin Verhoeven ,  Nicolas Nagel ,  Thomas Tatry ,  Dirk Caspary ,  Matthias Markert ,  Lothar Bauch ,  Stefan Blawid ,  Manuela Gutsch ,  Ludovic Lattard ,  Martin Roessiger ,  Mirko Vogt

IPC: H01L21/44 ,  G03F1/00 ,  H01L21/302

CPC classification number: H01L21/32139 ,  H01L21/0332 ,  H01L27/105 ,  H01L27/112

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract translation: 用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料 碳层顶部和设置在第一层顶部的硅层。 图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

公开(公告)号：US20080261395A1

公开(公告)日：2008-10-23

申请号：US11738086

申请日：2007-04-20

Applicant: Stefan Blawid ,  Ludovic Lattard ,  Roman Knoefler ,  Manuela Gutsch ,  David Pritchard ,  Martin Roessiger

Inventor： Stefan Blawid ,  Ludovic Lattard ,  Roman Knoefler ,  Manuela Gutsch ,  David Pritchard ,  Martin Roessiger

IPC: H01L23/48 ,  G03F1/00 ,  H01L21/44

CPC classification number: H01L27/0203 ,  H01L27/105 ,  H01L27/115

Abstract: Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned at an angle to the first structure, and the plurality of pad structures are intersecting at least one of the linear structures in the first structure. An electronic device with at least one semiconductor device, methods for manufacturing a semiconductor device and a mask system are also covered.

Abstract translation: 具有第一结构的半导体器件包括多个至少部分平行的线性结构，第二结构包括多个衬垫结构，至少部分地形成一组直线结构，弯曲结构，分段线性结构和分段弯曲 结构，其与第一结构成角度定位，并且多个垫结构在第一结构中与至少一个线性结构相交。 还包括具有至少一个半导体器件的电子器件，用于制造半导体器件的方法和掩模系统。

公开(公告)号：US08018070B2

公开(公告)日：2011-09-13

申请号：US11738086

申请日：2007-04-20

Applicant: Stefan Blawid ,  Ludovic Lattard ,  Roman Knoefler ,  Manuela Gutsch ,  David Pritchard ,  Martin Roessiger

Inventor： Stefan Blawid ,  Ludovic Lattard ,  Roman Knoefler ,  Manuela Gutsch ,  David Pritchard ,  Martin Roessiger

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/0203 ,  H01L27/105 ,  H01L27/115

Abstract: Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned at an angle to the first structure, and the plurality of pad structures are intersecting at least one of the linear structures in the first structure. An electronic device with at least one semiconductor device, methods for manufacturing a semiconductor device and a mask system are also covered.

Abstract translation: 具有第一结构的半导体器件包括多个至少部分平行的线性结构，第二结构包括多个衬垫结构，至少部分地形成一组直线结构，弯曲结构，分段线性结构和分段弯曲 结构，其与第一结构成角度定位，并且多个垫结构在第一结构中与至少一个线性结构相交。 还包括具有至少一个半导体器件的电子器件，用于制造半导体器件的方法和掩模系统。

公开(公告)号：US20080304029A1

公开(公告)日：2008-12-11

申请号：US11760295

申请日：2007-06-08

Applicant: Rainer Pforr ,  Thorsten Winkler ,  Ralf Ziebold ,  Wolfram Kostler ,  Jens Reichelt ,  Stefan Blawid ,  Sebastian Champigny ,  Manuel Vorwerk

Inventor： Rainer Pforr ,  Thorsten Winkler ,  Ralf Ziebold ,  Wolfram Kostler ,  Jens Reichelt ,  Stefan Blawid ,  Sebastian Champigny ,  Manuel Vorwerk

IPC: G03B27/14

CPC classification number: G03F7/705 ,  G03F1/36

Abstract: In a method of adjusting an optical parameter of an exposure apparatus, a photolithographic projection is performed using an exposure apparatus and using a layout pattern so as to provide measured layout data with different focus settings of the exposure apparatus. An optical model is provided including at least one optical parameter and a simulated image is created by using the optical model and the layout pattern. The optical model is optimized by modifying the optical parameter.

Abstract translation: 在调整曝光装置的光学参数的方法中，使用曝光装置进行光刻投影并使用布局图案，以便提供具有不同曝光装置的焦点设置的测量的布局数据。 提供了包括至少一个光学参数的光学模型，并且通过使用光学模型和布局图案来创建模拟图像。 通过修改光学参数优化光学模型。

公开(公告)号：US20070218627A1

公开(公告)日：2007-09-20

申请号：US11375912

申请日：2006-03-15

Applicant: Ludovic Lattard ,  Martin Roessiger ,  Lothar Bauch ,  Stefan Blawid ,  Manuela Gutsch

Inventor： Ludovic Lattard ,  Martin Roessiger ,  Lothar Bauch ,  Stefan Blawid ,  Manuela Gutsch

IPC: H01L21/8242

CPC classification number: H01L27/0203 ,  H01L27/1052 ,  H01L27/10891

Abstract: A method of forming a semiconductor device includes patterning a layer stack to form single conductive lines and single landing pads. Patterning of the layer stack includes two lithographic exposures using a set of two different photomasks. The landing pads are arranged at on side of an array region defined by a plurality of conductive lines. A set of photomasks used in the method of forming a semiconductor device includes a first photomask including patterns corresponding to the conductive lines and a second photomask including patterns corresponding to the landing pads. A semiconductor device includes conductive lines and landing pads connected with corresponding ones of said conductive lines wherein the landing pads are arranged in a staggered fashion at one side of an array region defined by a plurality of conductive lines.

Abstract translation: 形成半导体器件的方法包括图案化层叠以形成单个导电线和单个着陆焊盘。 层叠层的图案化包括使用一组两个不同光掩模的两次光刻曝光。 着陆焊盘布置在由多条导线限定的阵列区域的一侧。 在形成半导体器件的方法中使用的一组光掩模包括包括对应于导电线的图案的第一光掩模和包括对应于着陆焊盘的图案的第二光掩模。 半导体器件包括与对应的导电线连接的导电线和着陆焊盘，其中着陆焊盘以交错方式布置在由多条导线限定的阵列区域的一侧。