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公开(公告)号：US20070243707A1
公开(公告)日：2007-10-18
申请号：US11686501
申请日：2007-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert , Lothar Bauch , Stefan Blawid , Manuela Gutsch , Ludovic Lattard , Martin Roessiger , Mirko Vogt
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert , Lothar Bauch , Stefan Blawid , Manuela Gutsch , Ludovic Lattard , Martin Roessiger , Mirko Vogt
IPC分类号： H01L21/44 , G03F1/00 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译： 用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料 碳层顶部和设置在第一层顶部的硅层。 图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。
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公开(公告)号：US20070218627A1
公开(公告)日：2007-09-20
申请号：US11375912
申请日：2006-03-15
IPC分类号： H01L21/8242
CPC分类号： H01L27/0203 , H01L27/1052 , H01L27/10891
摘要： A method of forming a semiconductor device includes patterning a layer stack to form single conductive lines and single landing pads. Patterning of the layer stack includes two lithographic exposures using a set of two different photomasks. The landing pads are arranged at on side of an array region defined by a plurality of conductive lines. A set of photomasks used in the method of forming a semiconductor device includes a first photomask including patterns corresponding to the conductive lines and a second photomask including patterns corresponding to the landing pads. A semiconductor device includes conductive lines and landing pads connected with corresponding ones of said conductive lines wherein the landing pads are arranged in a staggered fashion at one side of an array region defined by a plurality of conductive lines.
摘要翻译： 形成半导体器件的方法包括图案化层叠以形成单个导电线和单个着陆焊盘。 层叠层的图案化包括使用一组两个不同光掩模的两次光刻曝光。 着陆焊盘布置在由多条导线限定的阵列区域的一侧。 在形成半导体器件的方法中使用的一组光掩模包括包括对应于导电线的图案的第一光掩模和包括对应于着陆焊盘的图案的第二光掩模。 半导体器件包括与对应的导电线连接的导电线和着陆焊盘，其中着陆焊盘以交错方式布置在由多条导线限定的阵列区域的一侧。
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3.发明申请METHOD AND SYSTEM FOR DETERMINING OVERLAP PROCESS WINDOWS IN SEMICONDUCTORS BY INSPECTION TECHNIQUES 有权通过检测技术确定半导体中重叠过程窗口的方法和系统公开(公告)号：US20140065734A1
公开(公告)日：2014-03-06
申请号：US13605060
申请日：2012-09-06
申请人： Lothar Bauch
发明人： Lothar Bauch
CPC分类号： H01L22/12 , G03F7/70633 , G03F7/7065 , G03F7/70683
摘要： The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished.
摘要翻译： 复杂半导体器件中重叠区域的形成是在常规测量和设计策略的基础上无法有效评估的一个关键方面。 为此，本公开提供了测量技术和系统，其中将重叠的设备图案转换成相同的材料层，从而形成可通过公认的缺陷检查技术访问的组合图案。 在对这些组合图案中的一些进行几何调制时，可以实现重叠处理窗口的系统评估。
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4.发明授权Stacked via with specially designed landing pad for integrated semiconductor structures 有权通过专门设计的集成半导体结构的着陆垫进行堆叠公开(公告)号：US06737748B2
公开(公告)日：2004-05-18
申请号：US10082554
申请日：2002-02-25
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are arranged one above the other. The metal islands project laterally beyond the vias to a significant extent on account of the line shortening effect. The vias arranged in layers lying one above the other are laterally offset with respect to one another. The landing pad of the invention is configured as an interconnect running between the vias. On account of the line shortening effect, which is less critical for longer tracks, contact areas provided at the ends of the interconnect do not have to be chosen to be as large as the square contact areas of conventional metal islands and can therefore be accommodated to save more space on a circuit layout to be miniaturized. The shrink factor of such a semiconductor structure is increased.
摘要翻译： 在堆叠过孔的制造中，引入了称为着陆焊盘的金属岛，用于在彼此上下布置的通孔之间的接触连接的目的。 由于线路缩短效应，金属岛在很大程度上突出超出通孔。 布置在一个彼此上下的层中的通孔相对于彼此横向偏移。 本发明的着陆垫被配置为在通孔之间运行的互连。 由于对较长轨道不那么关键的线路缩短效应，互连端部设置的接触区域不必被选择为与常规金属岛的方形接触面积一样大，因此可以容纳到 节省电路布局上的更多空间以实现小型化。 这种半导体结构的收缩率增加。
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5.发明授权Method for detecting positioning errors of circuit patterns during the transfer by means of a mask into layers of a substrate of a semiconductor wafer 失效用于在通过掩模转移到半导体晶片的衬底的层中的情况下检测电路图案的定位误差的方法公开(公告)号：US07084962B2
公开(公告)日：2006-08-01
申请号：US10951661
申请日：2004-09-29
CPC分类号： G03B27/32 , G03F7/70633
摘要： A method, suitable to photolithographie projection, for detecting the positioning errors of circuit patterns during the transfer by a mask into layers of a substrate of a semiconductor wafer. After the transfer of at least one multiple arrangement of a first test structure into at least one resist layer above the substrate, wherein the first test structure includes a first circuit pattern, at least one first overlay mark and at least one first micropatterned alignment mark, the values of a first positioning error of the first circuit patterns relative to the first overlay marks and the first micropatterned alignment marks are determined for each element of the at least one multiple arrangement.
摘要翻译： 一种适用于光刻投影的方法，用于检测在通过掩模转移到半导体晶片的衬底的层中的电路图案的定位误差。 在将第一测试结构的至少一个多重布置转移到衬底上方的至少一个抗蚀剂层中之后，其中第一测试结构包括第一电路图案，至少一个第一覆盖标记和至少一个第一微图案化对准标记， 针对至少一个多重布置的每个元件确定第一电路图案相对于第一覆盖标记和第一微图案化对准标记的第一定位误差的值。
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6.发明申请公开(公告)号：US20050153216A1
公开(公告)日：2005-07-14
申请号：US10998300
申请日：2004-11-26
申请人： Christian Crell , Lothar Bauch , Holger Moller , Ralf Ziebold
发明人： Christian Crell , Lothar Bauch , Holger Moller , Ralf Ziebold
CPC分类号： G03F1/36
摘要： Lithography mask having a structure for the fabrication of semiconductor components, in particular memory components, for a direction-dependent exposure device, featuring at least one auxiliary structure (1) for minimizing scattered light, the auxiliary structure (1) essentially being arranged in a low-resolution exposure direction of the direction-dependent exposure device (11, 11a, 11b) for the mask (10, 10a, 10b). A means for reducing scattered light is thus created by the auxiliary structure in a simple manner.
摘要翻译： 具有制造半导体部件的结构的光刻掩模，特别是用于依赖于方向的曝光装置的存储器部件，其特征在于至少一个用于使散射光最小化的辅助结构（1），所述辅助结构（1）基本上布置在 用于掩模（10,10a，10b）的方向依赖性曝光装置（11,11a，11b）的低分辨率曝光方向。 因此，辅助结构以简单的方式产生减少散射光的装置。
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7.发明授权Method and system for determining overlap process windows in semiconductors by inspection techniques 有权通过检测技术确定半导体重叠过程窗口的方法和系统公开(公告)号：US08940555B2
公开(公告)日：2015-01-27
申请号：US13605060
申请日：2012-09-06
申请人： Lothar Bauch
发明人： Lothar Bauch
CPC分类号： H01L22/12 , G03F7/70633 , G03F7/7065 , G03F7/70683
摘要： The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished.
摘要翻译： 复杂半导体器件中重叠区域的形成是在常规测量和设计策略的基础上无法有效评估的一个关键方面。 为此，本公开提供了测量技术和系统，其中将重叠的设备图案转换成相同的材料层，从而形成可通过公认的缺陷检查技术访问的组合图案。 在对这些组合图案中的一些进行几何调制时，可以实现重叠处理窗口的系统评估。
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8.发明申请Method for detecting positioning errors of circuit patterns during the transfer by means of a mask into layers of a substrate of a semiconductor wafer 失效用于在通过掩模转移到半导体晶片的衬底的层中的情况下检测电路图案的定位误差的方法公开(公告)号：US20050068515A1
公开(公告)日：2005-03-31
申请号：US10951661
申请日：2004-09-29
CPC分类号： G03B27/32 , G03F7/70633
摘要： The invention relates to a method for detecting the positioning errors of circuit patterns during the transfer by a mask into layers of a substrate of a semiconductor wafer. After the transfer of at least one multiple arrangement of a first test structure by means of photolithographic projection into at least one resist layer above the substrate, the first test structure having a first circuit pattern, at least one first overlay mark and at least one first micropatterned alignment mark, the values of a first positioning error of the first circuit patterns relative to the first overlay marks and the first micropatterned alignment marks are determined for each element of the at least one multiple arrangement.
摘要翻译： 本发明涉及一种用于在通过掩模转移到半导体晶片的衬底的层中时检测电路图案的定位误差的方法。 在通过光刻投影将至少一个第一测试结构的多个布置转移到衬底上方的至少一个抗蚀剂层中之后，第一测试结构具有第一电路图案，至少一个第一重叠标记和至少一个第一重叠标记 针对所述至少一个多重布置的每个元件确定所述第一电路图案相对于所述第一覆盖标记和所述第一微图案化对准标记的第一定位误差的值。
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9.发明授权Photolithographic mask having half tone main features and perpendicular half tone assist features 有权具有半色调主要特征和垂直半色调辅助功能的光刻掩模公开(公告)号：US07465522B2
公开(公告)日：2008-12-16
申请号：US10487911
申请日：2002-07-30
申请人： Lothar Bauch , Gerhard Kunkel , Hermann Sachse , Helmut Wurzer
发明人： Lothar Bauch , Gerhard Kunkel , Hermann Sachse , Helmut Wurzer
CPC分类号： G03F1/30
摘要： A photolithographic mask having half tone main features and perpendicular half tone assist features. One embodiment provides for the exposure of radiation-sensitive resist layers on semiconductor substrates. The mask has at least one radiation-transmissive substrate and at least one half-tone layer. The half-tone layer is used to provide main features, the main features being formed in such a way that the pattern formed by the main features is transferred into the resist layer when irradiated, and the half-tone layer is also used to provide assist features, the assist features being formed substantially perpendicular to the main features in such a way that the pattern formed by the assist features is not transferred into the resist layer when irradiated.
摘要翻译： 具有半色调主要特征和垂直半色调辅助功能的光刻掩模。 一个实施例提供了辐射敏感抗蚀剂层在半导体衬底上的曝光。 掩模具有至少一个辐射透射基底和至少一个半色调层。 半色调层用于提供主要特征，其主要特征是这样一种方式形成：当被照射时，由主要特征形成的图案被转移到抗蚀剂层中，半色调层也用于提供辅助 特征是辅助特征基本上垂直于主要特征形成，使得由辅助特征形成的图案在照射时不会转移到抗蚀剂层中。
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10.发明申请Method for transferring structures from a photomask into a photoresist layer 审中-公开将结构从光掩模转移到光致抗蚀剂层中的方法公开(公告)号：US20060257794A1
公开(公告)日：2006-11-16
申请号：US11408875
申请日：2006-04-21
申请人： Lars Voelkel , Lothar Bauch , Patrick Klingbeil , Joachim Herpe , Mirko Vogt
发明人： Lars Voelkel , Lothar Bauch , Patrick Klingbeil , Joachim Herpe , Mirko Vogt
IPC分类号： G03F7/26
CPC分类号： H01L21/0276
摘要： A method for transferring structures from a photomask into a photoresist layer is disclosed. In one embodiment, the method involves the patterning of a photoresist layer provided on a layer stack having a topology. In order to suppress standing waves in the photoresist layer and the resist swing effect, which causes variations in the feature sizes, a thin, conformal, organic antireflection layer is applied on the layer stack by means of a known CVD method. The photoresist layer can be patterned dimensionally accurately by means of the method. The method is particularly suitable for the patterning of photoresist layers which are provided for the implantation process of source/drain regions of transistors in semiconductor technology.
摘要翻译： 公开了一种将结构从光掩模转移到光致抗蚀剂层中的方法。 在一个实施例中，该方法涉及对具有拓扑的层叠层上提供的光致抗蚀剂层的图案化。 为了抑制光致抗蚀剂层中的驻波和导致特征尺寸变化的抗蚀剂摆动效应，通过已知的CVD方法将薄的共形有机抗反射层施加在层叠上。 通过该方法可以精确地对光致抗蚀剂层进行尺寸图案化。 该方法特别适用于为半导体技术中的晶体管的源极/漏极区域的注入工艺提供的光致抗蚀剂层的图案化。
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