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公开(公告)号：US09008252B2
公开(公告)日：2015-04-14
申请号：US13650848
申请日：2012-10-12
CPC分类号： H04L7/0016 , H03C3/0925 , H03C3/0941 , H03C3/0975 , H03L7/00 , H03L7/0814
摘要： A circuit includes an oscillator, a variable phase adjuster and a feedback loop. The oscillator is configured to provide an RF signal, wherein the oscillator is configured to operate in a free-running mode of operation. The variable phase adjuster is configured to provide a phase adjusted signal, a phase of which is shifted with respect to a phase of an output signal of the oscillator, or with respect to a phase of a signal derived from the output signal of the oscillator. The feedback loop is configured to provide a control value for controlling the variable phase adjuster based on the phase adjusted signal and a reference oscillator signal to counteract a phase error of the phase adjusted signal.
摘要翻译： 电路包括振荡器，可变相位调节器和反馈回路。 振荡器被配置为提供RF信号，其中振荡器被配置为以自由运行的操作模式操作。 可变相位调整器被配置为提供相位调整信号，其相位相对于振荡器的输出信号的相位偏移，或相对于从振荡器的输出信号导出的信号的相位移位。 反馈回路被配置为提供用于基于相位调整信号和参考振荡器信号来控制可变相位调整器的控制值，以抵消相位调整信号的相位误差。
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2.发明授权Non-linear-error correction in fractional-N digital PLL frequency synthesizer 有权分数N数字PLL频率合成器中的非线性误差校正公开(公告)号：US08791733B2
公开(公告)日：2014-07-29
申请号：US13645760
申请日：2012-10-05
IPC分类号： H03L7/06
CPC分类号： H03L7/1976 , H03L7/085
摘要： The present disclosure relates to a frequency synthesizer. The frequency synthesizer includes a phase comparator having first and second input nodes. The first input node receives a reference signal having a reference frequency. A channel control block has an input that receives a channel word and an output coupled to the second input node of the phase comparator. A local oscillator (LO) output node provides an LO signal having an LO frequency based on the reference frequency and the channel word. A feedback back couples the LO output node to the second input node of the phase comparator through the channel control block. A non-linear error correction element is operably coupled on a coupling path extending between the phase comparator and the DCO.
摘要翻译： 本公开涉及频率合成器。 频率合成器包括具有第一和第二输入节点的相位比较器。 第一输入节点接收具有参考频率的参考信号。 信道控制块具有接收信道字的输入和耦合到相位比较器的第二输入节点的输出。 本地振荡器（LO）输出节点基于参考频率和通道字提供具有LO频率的LO信号。 反馈反馈通过信道控制块将LO输出节点耦合到相位比较器的第二输入节点。 非线性误差校正元件可操作地耦合在相位比较器和DCO之间延伸的耦合路径上。
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3.发明申请Non-Linear-Error Correction in Fractional-N Digital PLL Frequency Synthesizer 有权分数N数字PLL频率合成器中的非线性误差校正公开(公告)号：US20140097875A1
公开(公告)日：2014-04-10
申请号：US13645760
申请日：2012-10-05
IPC分类号： H03B21/00
CPC分类号： H03L7/1976 , H03L7/085
摘要： The present disclosure relates to a frequency synthesizer. The frequency synthesizer includes a phase comparator having first and second input nodes. The first input node receives a reference signal having a reference frequency. A channel control block has an input that receives a channel word and an output coupled to the second input node of the phase comparator. A local oscillator (LO) output node provides an LO signal having an LO frequency based on the reference frequency and the channel word. A feedback back couples the LO output node to the second input node of the phase comparator through the channel control block. A non-linear error correction element is operably coupled on a coupling path extending between the phase comparator and the DCO.
摘要翻译： 本公开涉及频率合成器。 频率合成器包括具有第一和第二输入节点的相位比较器。 第一输入节点接收具有参考频率的参考信号。 信道控制块具有接收信道字的输入和耦合到相位比较器的第二输入节点的输出。 本地振荡器（LO）输出节点基于参考频率和通道字提供具有LO频率的LO信号。 反馈反馈通过信道控制块将LO输出节点耦合到相位比较器的第二输入节点。 非线性误差校正元件可操作地耦合在相位比较器和DCO之间延伸的耦合路径上。
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公开(公告)号：US20140105343A1
公开(公告)日：2014-04-17
申请号：US13650848
申请日：2012-10-12
IPC分类号： H04L7/00
CPC分类号： H04L7/0016 , H03C3/0925 , H03C3/0941 , H03C3/0975 , H03L7/00 , H03L7/0814
摘要： A circuit includes an oscillator, a variable phase adjuster and a feedback loop. The oscillator is configured to provide an RF signal, wherein the oscillator is configured to operate in a free-running mode of operation. The variable phase adjuster is configured to provide a phase adjusted signal, a phase of which is shifted with respect to a phase of an output signal of the oscillator, or with respect to a phase of a signal derived from the output signal of the oscillator. The feedback loop is configured to provide a control value for controlling the variable phase adjuster based on the phase adjusted signal and a reference oscillator signal to counteract a phase error of the phase adjusted signal.
摘要翻译： 电路包括振荡器，可变相位调节器和反馈回路。 所述振荡器被配置为提供RF信号，其中所述振荡器被配置为以自由运行的操作模式操作。 可变相位调整器被配置为提供相位调整信号，其相位相对于振荡器的输出信号的相位偏移，或相对于从振荡器的输出信号导出的信号的相位移位。 反馈回路被配置为提供用于基于相位调整信号和参考振荡器信号来控制可变相位调整器的控制值，以抵消相位调整信号的相位误差。
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公开(公告)号：US08598929B1
公开(公告)日：2013-12-03
申请号：US13664536
申请日：2012-10-31
申请人： Christian Wicpalek , Thomas Mayer
发明人： Christian Wicpalek , Thomas Mayer
IPC分类号： H03L7/06
CPC分类号： H03L7/1075 , H03L7/093 , H03L7/095 , H03L7/101 , H03L7/104
摘要： The disclosed invention relates to a digital phase locked loop having a switchable digital loop filter configured to selectively operate at different levels of resolution. The digital phase locked loop has a phase frequency detector that determines a phase difference between a reference signal and a feedback signal and to convert the phase difference to a digital word. A digital loop filter filters the digital word to generate a control word. A bit shift network modifies the digital word in a manner that switches the resolution of the digital loop filter between two or more distinct resolution states that comprise a bit sequence located at different positions in the digital word. The two or more distinct resolution states allow the digital loop filter to provide a low resolution (high amplitude) for a settling state of operation and a high resolution (low amplitude) for a locked state of operation.
摘要翻译： 所公开的本发明涉及一种具有可切换数字环路滤波器的数字锁相环，其被配置为选择性地以不同的分辨率水平进行操作。 数字锁相环具有相位频率检测器，其确定参考信号和反馈信号之间的相位差，并将相位差转换为数字字。 数字环路滤波器对数字字进行滤波以产生控制字。 位移网络以使数字环路滤波器的分辨率在两个或多个不同分辨率状态之间切换的方式修改数字字，该状态包括位于数字字中的不同位置的位序列。 两个或更多个不同的分辨率状态允许数字环路滤波器为操作的建立状态提供低分辨率（高幅度），并且对于锁定操作状态提供高分辨率（低幅度）。
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6.发明授权Digital wideband closed loop phase modulator with modulation gain calibration 有权带调制增益校准的数字宽带闭环相位调制器公开(公告)号：US09225562B2
公开(公告)日：2015-12-29
申请号：US13405583
申请日：2012-02-27
CPC分类号： H04L25/03343 , H04L27/2003 , H04L27/2032 , H04L27/368
摘要： One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.
摘要翻译： 本发明的一个实施例涉及一种具有锁相环和自适应控制的调制系统。 相位锁定环被配置为接收输入信号和自适应信号。 输入信号是未调制信号，例如相位分量或相位信号。 锁相环也被配置为提供误差信号和输出信号。 误差信号表示一个或多个调制误差。 输出信号是使用自适应信号校正的输入信号的调制版本，以减轻一个或多个调制误差。
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公开(公告)号：US08098104B2
公开(公告)日：2012-01-17
申请号：US12578105
申请日：2009-10-13
CPC分类号： H03L7/099 , H03B2200/0092 , H03L7/093 , H03L7/1976 , H03L2207/05
摘要： A device may include an oscillator circuit, a control circuit, a frequency detector circuit, and a processor circuit. The oscillator circuit may include a frequency control input to output an oscillator signal. The frequency of the oscillator signal depends on an input signal applied to the frequency control input. The control circuit is configured to apply a first input signal value, a second input signal value, and a third input signal value to the frequency control input. The frequency detector circuit is configured to detect the first frequency value of the oscillator signal when the first input signal value is applied to the frequency control input, a second frequency value of the oscillator signal when the second input signal value is applied to the frequency control input, and a third frequency value of the oscillator signal when the third input signal value is applied to the frequency control input.
摘要翻译： 设备可以包括振荡器电路，控制电路，频率检测器电路和处理器电路。 振荡器电路可以包括用于输出振荡器信号的频率控制输入。 振荡器信号的频率取决于施加到频率控制输入的输入信号。 控制电路被配置为向频率控制输入施加第一输入信号值，第二输入信号值和第三输入信号值。 频率检测器电路被配置为当第一输入信号值被施加到频率控制输入时检测振荡器信号的第一频率值，当第二输入信号值被施加到频率控制时，振荡器信号的第二频率值 输入和第三频率值，当第三输入信号值被施加到频率控制输入时。
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8.发明申请DIGITAL WIDEBAND CLOSED LOOP PHASE MODULATOR WITH MODULATION GAIN CALIBRATION 有权数字宽带闭环相位调制器，具有调制增益校准公开(公告)号：US20130223564A1
公开(公告)日：2013-08-29
申请号：US13405583
申请日：2012-02-27
IPC分类号： H04L27/20
CPC分类号： H04L25/03343 , H04L27/2003 , H04L27/2032 , H04L27/368
摘要： One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.
摘要翻译： 本发明的一个实施例涉及一种具有锁相环和自适应控制的调制系统。 相位锁定环被配置为接收输入信号和自适应信号。 输入信号是未调制信号，例如相位分量或相位信号。 锁相环也被配置为提供误差信号和输出信号。 误差信号表示一个或多个调制误差。 输出信号是使用自适应信号校正的输入信号的调制版本，以减轻一个或多个调制误差。
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9.发明授权Phase/frequency detector, phase locked loop, method for phase/frequency detection and method for generating an oscillator signal 有权相位/频率检测器，锁相环，相位/频率检测方法以及产生振荡器信号的方法公开(公告)号：US07592874B2
公开(公告)日：2009-09-22
申请号：US11925539
申请日：2007-10-26
CPC分类号： H03L7/085 , H03D13/001 , H03L7/0991 , H03L7/18 , H03L2207/50
摘要： A phase/frequency detector has a modulo counter for outputting a counter word with a predetermined word length depending on an oscillator signal. In addition, a modulo integrator for outputting an integrator word with the predetermined word length as a function of integration of a channel word is provided. The phase/frequency detector also has a difference element for outputting a phase error word with the predetermined word length as a function of a difference between the counter word and the integrator word.
摘要翻译： 相位/频率检测器具有模计数器，用于根据振荡器信号输出具有预定字长的计数器字。 另外，提供了用于输出具有作为通道字的积分的函数的预定字长的积分器字的模积分器。 相位/频率检测器还具有差分元件，用于输出具有预定字长的相位误差字作为计数器字和积分器字之差的函数。
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10.发明申请Phase Locked Loop, Transceiver Device and Method for Generating an Oscillator Signal 有权锁相环，收发器装置和产生振荡器信号的方法公开(公告)号：US20080106341A1
公开(公告)日：2008-05-08
申请号：US11925379
申请日：2007-10-26
摘要： A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.
摘要翻译： 锁相环具有受控振荡器，用于根据控制信号输出振荡器信号。 比较器从参考频率信号和从振荡器信号导出的反馈信号之间的比较产生比较结果。 锁相环还具有用于对比较结果进行滤波和从比较结果导出控制信号的滤波器块，其中滤波器块具有环路滤波器和用于至少一个第一干扰频率的频率选择衰减的抑制滤波器 在比较结果中。
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