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公开(公告)号：US07616517B1
公开(公告)日：2009-11-10
申请号：US12167431
申请日：2008-07-03
CPC分类号： G11C11/417 , G06F1/3203 , G06F1/3287 , G11C5/14 , G11C5/144 , G11C5/148 , Y02D10/171
摘要： A circuit which includes an IP cell having a function select input signal line, combinatorial logic having an output connected to the function select input signal line of the IP cell, a configuration register having an output connected to an input of the combinatorial logic, wherein a high/low input signal line is also connected to the combinatorial logic, wherein the circuit provided that the configuration register receives configuration data during a start-up sequence, and configuration data is held by the combinatorial logic as the configuration register powers down during a functional mode.
摘要翻译： 一种包括具有功能选择输入信号线的IP单元的电路，组合逻辑具有连接到IP单元的功能选择输入信号线的输出，配置寄存器，具有连接到组合逻辑的输入的输出，其中a 高/低输入信号线也连接到组合逻辑，其中电路提供配置寄存器在启动序列期间接收配置数据，并且配置数据由组态逻辑保持，因为配置寄存器在功能性 模式。
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公开(公告)号：US08078926B2
公开(公告)日：2011-12-13
申请号：US12558611
申请日：2009-09-14
IPC分类号： G01R31/28
CPC分类号： G01R31/31701 , G01R31/318541
摘要： An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.
摘要翻译： 对具有用于仅在测试使能线处于逻辑高值时才能进行集成电路的电气测试的测试使能线的类型的集成电路的改进以及仅在集成电路的电测试期间使用的输出线 电路，其中改进是当测试使能线处于逻辑低值时禁止输出线路中的状态改变的开关电路。 以这种方式，输出线在集成电路的功能使用期间不切换，并且不能成为在集成电路的功能使用期间由数据线承载的数据信号的侵略者。 此外，这些非开关输出线可以用作在数据线之间运行的保护迹线，进一步将数据线彼此电隔离。 此外，由于在集成电路的功能使用期间不切换，集成电路的总体功耗降低。
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公开(公告)号：US20110066905A1
公开(公告)日：2011-03-17
申请号：US12558611
申请日：2009-09-14
IPC分类号： G06F11/00
CPC分类号： G01R31/31701 , G01R31/318541
摘要： An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.
摘要翻译： 对具有用于仅在测试使能线处于逻辑高值时才能进行集成电路的电气测试的测试使能线的类型的集成电路的改进以及仅在集成电路的电测试期间使用的输出线 电路，其中改进是当测试使能线处于逻辑低值时禁止输出线路中的状态改变的开关电路。 以这种方式，输出线在集成电路的功能使用期间不切换，并且不能成为在集成电路的功能使用期间由数据线承载的数据信号的侵略者。 此外，这些非开关输出线可以用作在数据线之间运行的保护迹线，进一步将数据线彼此电隔离。 此外，由于在集成电路的功能使用期间不切换，集成电路的总体功耗降低。
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公开(公告)号：US20100153824A1
公开(公告)日：2010-06-17
申请号：US12335096
申请日：2008-12-15
申请人： Claus Pribbernow , Stephan Habel
发明人： Claus Pribbernow , Stephan Habel
CPC分类号： H03K3/0375 , G06F11/1008
摘要： In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low.
摘要翻译： 在一个实施例中，电路具有多个触发器，门控时钟输入由使能信号控制，其中时钟信号被选通以减少电路的功耗。 该电路具有错误检测和校正（EDC）模块，当使能信号为低电平时，该模块有效，以检测和纠正触发器的软错误。 EDC模块基于触发器的数据输出产生并存储纠错码。 然后，EDC模块将存储的纠错码与当前生成的纠错码进行比较，如果它们不相同，则EDC（a）确定（i）已发生软错误，以及（ii） 触发器出现软错误，（b）翻转相应的纠错信号，以在使能信号为低电平时提供正确的相应输出信号。
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公开(公告)号：US08365049B2
公开(公告)日：2013-01-29
申请号：US12335096
申请日：2008-12-15
申请人： Claus Pribbernow , Stephan Habel
发明人： Claus Pribbernow , Stephan Habel
IPC分类号： H03M13/00
CPC分类号： H03K3/0375 , G06F11/1008
摘要： In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low.
摘要翻译： 在一个实施例中，电路具有多个触发器，门控时钟输入由使能信号控制，其中时钟信号被选通以减少电路的功耗。 该电路具有错误检测和校正（EDC）模块，当使能信号为低电平时，该模块有效，以检测和纠正触发器的软错误。 EDC模块基于触发器的数据输出产生并存储纠错码。 然后，EDC模块将存储的纠错码与当前生成的纠错码进行比较，如果它们不相同，则EDC（a）确定（i）已发生软错误，以及（ii） 触发器出现软错误，（b）翻转相应的纠错信号，以在使能信号为低电平时提供正确的相应输出信号。
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公开(公告)号：US20110084726A1
公开(公告)日：2011-04-14
申请号：US12969424
申请日：2010-12-15
申请人： Stephan Habel , Stefan G. Block
发明人： Stephan Habel , Stefan G. Block
IPC分类号： H03K19/173
CPC分类号： H03K5/135 , G01R31/31858 , H03K3/011
摘要： A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.
摘要翻译： 提供了一种方法和装置，用于将值存储在电路的处理寄存器中，该值指示制造电路的处理的强度，并且调整施加到由所述电路的同步存储元件接收的数据信号的输入延迟 电路基于存储值。
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7.发明授权Method and computer program for configuring an integrated circuit design for static timing analysis 有权用于配置静态时序分析的集成电路设计的方法和计算机程序公开(公告)号：US07958473B2
公开(公告)日：2011-06-07
申请号：US12117760
申请日：2008-05-09
申请人： Juergen Dirks , Udo Elsholz , Stephan Habel , Ansgar Bambynek
发明人： Juergen Dirks , Udo Elsholz , Stephan Habel , Ansgar Bambynek
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The module data is configured for the module from the selected configuration item into a static timing analysis scenario for performing a static timing analysis of the configured module data.
摘要翻译： 用于配置用于静态时序分析的集成电路设计的方法和计算机程序包括在集成电路设计中接收表示模块层级的模块数据。 从至少一个模块的配置项列表中选择配置项。 模块数据被配置为模块从所选配置项到静态时序分析场景，用于执行配置的模块数据的静态时序分析。
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公开(公告)号：US07944237B2
公开(公告)日：2011-05-17
申请号：US12969424
申请日：2010-12-15
申请人： Stephan Habel , Stefan G. Block
发明人： Stephan Habel , Stefan G. Block
IPC分类号： H03K19/173 , H03K19/00
CPC分类号： H03K5/135 , G01R31/31858 , H03K3/011
摘要： A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.
摘要翻译： 提供了一种方法和装置，用于将值存储在电路的处理寄存器中，该值指示制造电路的处理的强度，并且调整施加到由所述电路的同步存储元件接收的数据信号的输入延迟 电路基于存储值。
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9.发明授权公开(公告)号：US07514974B2
公开(公告)日：2009-04-07
申请号：US11736931
申请日：2007-04-18
申请人： Stefan G. Block , Stephan Habel
发明人： Stefan G. Block , Stephan Habel
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/0805
摘要： An apparatus and method are provided for powering an integrated circuit chip with a supply voltage generated externally to the chip. An on-chip clock signal is generated with a ring oscillator fabricated on the integrated circuit chip. The supply voltage is altered as a function of a difference between a frequency of the on-chip clock signal and a reference clock frequency.
摘要翻译： 提供了一种装置和方法，用于为集成电路芯片提供在芯片外部产生的电源电压供电。 在集成电路芯片上制造的环形振荡器产生片上时钟信号。 电源电压根据片内时钟信号的频率和参考时钟频率之间的差异而改变。
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公开(公告)号：US07880498B2
公开(公告)日：2011-02-01
申请号：US11944488
申请日：2007-11-23
申请人： Stephan Habel , Stefan G. Block
发明人： Stephan Habel , Stefan G. Block
IPC分类号： H03K19/173
CPC分类号： H03K5/135 , G01R31/31858 , H03K3/011
摘要： A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.
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