公开(公告)号：US20070164356A1

公开(公告)日：2007-07-19

申请号：US11332564

申请日：2006-01-13

申请人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US20070111463A1

公开(公告)日：2007-05-17

申请号：US11620663

申请日：2007-01-06

申请人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/337 ,  H01L27/12 ,  H01L21/76

CPC分类号： H01L21/76259 ,  Y10S438/967

摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

摘要翻译： 提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。 该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。 该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。 根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

公开(公告)号：US20050153487A1

公开(公告)日：2005-07-14

申请号：US11039602

申请日：2005-01-19

申请人： Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12 ,  H01L21/00

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

摘要： A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

摘要翻译： 提供了使用SIMOX和Ge相互扩散形成基本上松弛的，优质的绝缘体上硅衬底材料的方法。 该方法包括首先将离子注入到含Si衬底中以在含Si衬底中形成植入离子富集区。 注入离子富集区具有足够的离子浓度，使得在随后的高温退火期间形成耐Ge扩散的阻挡层。 接下来，在含Si衬底的表面上形成Ge含有层，然后在允许形成阻挡层和Ge的相互扩散的温度下进行加热步骤，从而形成基本上松弛的单晶SiGe层 阻挡层顶部。

公开(公告)号：US20060003555A1

公开(公告)日：2006-01-05

申请号：US10883887

申请日：2004-07-02

申请人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  C30B1/00 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L21/76259 ,  Y10S438/967

摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

公开(公告)号：US20050221591A1

公开(公告)日：2005-10-06

申请号：US10818572

申请日：2004-04-06

申请人： Stephen Bedell ,  Huajie Chen ,  Joel de Souza ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Huajie Chen ,  Joel de Souza ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： C30B1/00 ,  H01L21/20 ,  H01L21/3063 ,  H01L21/36 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L21/3063 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02658

摘要： A method of forming a high-quality relaxed SiGe alloy layer on a bulk Si-containing substrate is provided. The method of the present invention includes growing a strained SiGe alloy layer on a Si-containing substrate that has a porous Si-containing layer at or near the surface of the Si-containing substrate. The porous layer is formed by an electrolytic anodization process. The pores create free volume below the strained SiGe layer which can serve to accommodate strain relaxation during SiGe deposition or a subsequent heating step. The subsequent heating step is optional and is performed to further increase the relaxation of the SiGe alloy layer. The buried porous structure allows for a unique relaxation mechanism compared to prior art methods.

摘要翻译： 提供了在体积含Si衬底上形成高品质的弛豫SiGe合金层的方法。 本发明的方法包括在含Si衬底上生长应变SiGe合金层，该Si基合金层在含Si衬底的表面处或附近具有多孔含Si层。 多孔层通过电解阳极氧化处理形成。 孔隙在应变SiGe层之下产生自由体积，其可用于在SiGe沉积或随后的加热步骤期间适应应变松弛。 随后的加热步骤是可选的并且进行以进一步增加SiGe合金层的松弛。 与现有技术方法相比，埋入的多孔结构允许独特的松弛机制。

公开(公告)号：US20070257315A1

公开(公告)日：2007-11-08

申请号：US11417846

申请日：2006-05-04

申请人： Stephen Bedell ,  Joel De Souza ,  Zhibin Ren ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Joel De Souza ,  Zhibin Ren ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger ,  Ghavam Shahidi

IPC分类号： H01L21/8234

CPC分类号： H01L21/26513 ,  H01L21/2658 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

摘要翻译： 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源极/漏极（S / D）区域的潜在问题）的方法， 以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

公开(公告)号：US20060011906A1

公开(公告)日：2006-01-19

申请号：US10890765

申请日：2004-07-14

申请人： Stephen Bedell ,  Huajie Chen ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Huajie Chen ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L29/06

CPC分类号： H01L21/26506 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/2658

摘要： A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed. The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.

摘要翻译： 公开了一种用于制造具有减小的平面缺陷密度的基本上松弛的SiGe合金层的方法。 本发明的方法包括在含Si基材的表面上形成应变的含Ge层; 在含锗层/含Si衬底界面处或下方注入离子，并加热以形成具有减小的平面缺陷密度的基本上松弛的SiGe合金层。 还提供了具有具有减小的平面缺陷密度的SiGe层以及含有该SiGe层的异质结构的基本上松弛的绝缘体上硅衬底材料。

公开(公告)号：US20050095803A1

公开(公告)日：2005-05-05

申请号：US10984212

申请日：2004-11-09

申请人： Stephen Bedell ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

摘要： A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing substrate. The implant rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

公开(公告)号：US20050090080A1

公开(公告)日：2005-04-28

申请号：US10993270

申请日：2004-11-19

申请人： Keith Fogel ,  Mark Hakey ,  Steven Holmes ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Keith Fogel ,  Mark Hakey ,  Steven Holmes ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

摘要： Methods for forming a patterned SOI region in a Si-containing substrate is provided which has geometries of about 0.25 μm or less. Specifically, one method includes the steps of: forming a patterned dielectric mask on a surface of a Si-containing substrate, wherein the patterned dielectric mask includes vertical edges that define boundaries for at least one opening which exposes a portion of the Si-containing substrate; implanting oxygen ions through the at least one opening removing the mask and forming a Si layer on at least the exposed surfaces of the Si-containing substrate; and annealing at a temperature of about 1250° C. or above and in an oxidizing ambient so as to form at least one discrete buried oxide region in the Si-containing substrate. In one embodiment, the mask is not removed until after the annealing step; and in another embodiment, the Si-containing layer is formed after annealing and mask removal.

摘要翻译： 提供了在含Si衬底中形成图案化SOI区的方法，其具有约0.25μm或更小的几何形状。 具体而言，一种方法包括以下步骤：在含Si衬底的表面上形成图案化电介质掩模，其中，图案化电介质掩模包括垂直边缘，其限定至少一个露出一部分含Si衬底的开口的边界 ; 通过所述至少一个开口注入氧离子，去除所述掩模并在至少所述含Si衬底的暴露表面上形成Si层; 并在约1250℃或更高的温度下和在氧化环境中进行退火，以便在含Si衬底中形成至少一个离散的掩埋氧化物区域。 在一个实施例中，直到退火步骤之后，掩模才被去除; 并且在另一个实施方案中，在退火和掩模去除之后形成含Si层。

公开(公告)号：US20080050887A1

公开(公告)日：2008-02-28

申请号：US11924207

申请日：2007-10-25

申请人： Tze-chiang Chen ,  Guy Cohen ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Tze-chiang Chen ,  Guy Cohen ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/30

CPC分类号： H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

摘要翻译： 提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。 在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。