公开(公告)号：US20050221591A1

公开(公告)日：2005-10-06

申请号：US10818572

申请日：2004-04-06

申请人： Stephen Bedell ,  Huajie Chen ,  Joel de Souza ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Huajie Chen ,  Joel de Souza ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： C30B1/00 ,  H01L21/20 ,  H01L21/3063 ,  H01L21/36 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L21/3063 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02658

摘要： A method of forming a high-quality relaxed SiGe alloy layer on a bulk Si-containing substrate is provided. The method of the present invention includes growing a strained SiGe alloy layer on a Si-containing substrate that has a porous Si-containing layer at or near the surface of the Si-containing substrate. The porous layer is formed by an electrolytic anodization process. The pores create free volume below the strained SiGe layer which can serve to accommodate strain relaxation during SiGe deposition or a subsequent heating step. The subsequent heating step is optional and is performed to further increase the relaxation of the SiGe alloy layer. The buried porous structure allows for a unique relaxation mechanism compared to prior art methods.

摘要翻译： 提供了在体积含Si衬底上形成高品质的弛豫SiGe合金层的方法。 本发明的方法包括在含Si衬底上生长应变SiGe合金层，该Si基合金层在含Si衬底的表面处或附近具有多孔含Si层。 多孔层通过电解阳极氧化处理形成。 孔隙在应变SiGe层之下产生自由体积，其可用于在SiGe沉积或随后的加热步骤期间适应应变松弛。 随后的加热步骤是可选的并且进行以进一步增加SiGe合金层的松弛。 与现有技术方法相比，埋入的多孔结构允许独特的松弛机制。

公开(公告)号：US20070164356A1

公开(公告)日：2007-07-19

申请号：US11332564

申请日：2006-01-13

申请人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US20070111463A1

公开(公告)日：2007-05-17

申请号：US11620663

申请日：2007-01-06

申请人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/337 ,  H01L27/12 ,  H01L21/76

CPC分类号： H01L21/76259 ,  Y10S438/967

摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

摘要翻译： 提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。 该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。 该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。 根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

公开(公告)号：US20050153487A1

公开(公告)日：2005-07-14

申请号：US11039602

申请日：2005-01-19

申请人： Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12 ,  H01L21/00

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

摘要： A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

摘要翻译： 提供了使用SIMOX和Ge相互扩散形成基本上松弛的，优质的绝缘体上硅衬底材料的方法。 该方法包括首先将离子注入到含Si衬底中以在含Si衬底中形成植入离子富集区。 注入离子富集区具有足够的离子浓度，使得在随后的高温退火期间形成耐Ge扩散的阻挡层。 接下来，在含Si衬底的表面上形成Ge含有层，然后在允许形成阻挡层和Ge的相互扩散的温度下进行加热步骤，从而形成基本上松弛的单晶SiGe层 阻挡层顶部。

公开(公告)号：US20060003555A1

公开(公告)日：2006-01-05

申请号：US10883887

申请日：2004-07-02

申请人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  C30B1/00 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L21/76259 ,  Y10S438/967

摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

公开(公告)号：US20060011906A1

公开(公告)日：2006-01-19

申请号：US10890765

申请日：2004-07-14

申请人： Stephen Bedell ,  Huajie Chen ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Huajie Chen ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L29/06

CPC分类号： H01L21/26506 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/2658

摘要： A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed. The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.

摘要翻译： 公开了一种用于制造具有减小的平面缺陷密度的基本上松弛的SiGe合金层的方法。 本发明的方法包括在含Si基材的表面上形成应变的含Ge层; 在含锗层/含Si衬底界面处或下方注入离子，并加热以形成具有减小的平面缺陷密度的基本上松弛的SiGe合金层。 还提供了具有具有减小的平面缺陷密度的SiGe层以及含有该SiGe层的异质结构的基本上松弛的绝缘体上硅衬底材料。

公开(公告)号：US20070257315A1

公开(公告)日：2007-11-08

申请号：US11417846

申请日：2006-05-04

申请人： Stephen Bedell ,  Joel De Souza ,  Zhibin Ren ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Joel De Souza ,  Zhibin Ren ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger ,  Ghavam Shahidi

IPC分类号： H01L21/8234

CPC分类号： H01L21/26513 ,  H01L21/2658 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

摘要翻译： 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源极/漏极（S / D）区域的潜在问题）的方法， 以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

公开(公告)号：US20050095803A1

公开(公告)日：2005-05-05

申请号：US10984212

申请日：2004-11-09

申请人： Stephen Bedell ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

摘要： A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing substrate. The implant rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

公开(公告)号：US20070105350A1

公开(公告)日：2007-05-10

申请号：US11619040

申请日：2007-01-02

申请人： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

发明人： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

IPC分类号： C30B1/00 ,  H01L21/20

CPC分类号： H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.

摘要翻译： 描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。 使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。 薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。 这可以通过在高温下使用内部氧化来实现。 以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

公开(公告)号：US20050048778A1

公开(公告)日：2005-03-03

申请号：US10654232

申请日：2003-09-03

申请人： Stephen Bedell ,  Huajie Chen ,  Keith Fogel ,  Devendra Sadana

发明人： Stephen Bedell ,  Huajie Chen ,  Keith Fogel ,  Devendra Sadana

IPC分类号： H01L29/161 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04 ,  C30B1/00 ,  C30B3/00 ,  C30B5/00 ,  C30B28/02 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/7624 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/24917

摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

摘要翻译： 在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化 温度。 因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。