利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.025 秒)

    STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
    1.
    发明申请
    STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
    应变器件，制造方法和设计结构

    公开(公告)号：US20120216158A1

    公开(公告)日：2012-08-23

    申请号：US13457932

    申请日：2012-04-27

    申请人： Stephen W. BEDELL ,  Kangguo CHENG ,  Bruce B. DORIS ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Katherine L. SAENGER

    发明人： Stephen W. BEDELL ,  Kangguo CHENG ,  Bruce B. DORIS ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Katherine L. SAENGER

    IPC分类号： G06F17/50 ,  H01L27/12

    CPC分类号： H01L21/84 ,  H01L21/823807

    摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.

    摘要翻译： 应变Si和应变SiGe绝缘体器件，制造方法和设计结构。 该方法包括在绝缘体上硅晶片上生长SiGe层。 该方法还包括将SiGe层图案化成PFET和NFET区域，使得PFET和NFET区域中的SiGe层中的应变被放宽。 该方法还包括通过离子注入直接在SiGe层下面的Si层的至少一部分而非晶化。 该方法还包括进行热退火以使Si层重结晶，使得晶格常数与弛豫SiGe的晶格常数相匹配，从而在NFET区域上产生拉伸应变。 该方法还包括从NFET区域去除SiGe层。 该方法还包括执行Ge工艺以将PFET区域中的Si层转换为压缩应变的SiGe。

    FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION
    2.
    发明申请
    FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION 有权
    通过离子植入形成嵌入式压力器

    公开(公告)号：US20120313168A1

    公开(公告)日：2012-12-13

    申请号：US13155878

    申请日：2011-06-08

    申请人： Kangguo CHENG ,  Bruce B. DORIS ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Ghavam G. SHAHIDI

    发明人： Kangguo CHENG ,  Bruce B. DORIS ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Ghavam G. SHAHIDI

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78654

    摘要： An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.

    摘要翻译： 极薄的绝缘体上硅晶体管包括在衬底上方的掩埋氧化物层。 掩埋氧化物层例如具有小于50nm的厚度。 硅层在掩埋氧化物层之上。 硅层上的栅极叠层包括至少形成在硅层上的栅极电介质和形成在栅极电介质上的栅极导体。 栅极间隔物在硅层上具有第一部分，第二部分邻近栅极堆叠。 第一升高的源极/漏极区域和第二升高的源极/漏极区域各自具有包括硅层的一部分的第一部分和与栅极间隔物相邻的第二部分。 至少部分地在衬底内形成至少一个嵌入式应力器，其在硅层中形成的硅沟道区域上施加预定的应力。

    METHOD FOR FABRICATING JUNCTIONLESS TRANSISTOR
    3.
    发明申请
    METHOD FOR FABRICATING JUNCTIONLESS TRANSISTOR 审中-公开
    用于制造无连接晶体管的方法

    公开(公告)号：US20130078777A1

    公开(公告)日：2013-03-28

    申请号：US13618054

    申请日：2012-09-14

    申请人： Kangguo CHENG ,  Bruce B. DORIS ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Tak H. NING

    发明人： Kangguo CHENG ,  Bruce B. DORIS ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Tak H. NING

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78654 ,  H01L29/78696

    摘要： A method is provided for fabricating a transistor. According to the method, a doped material layer is formed on a semiconductor layer, and dopant is diffused from the doped material layer into the semiconductor layer to form a graded dopant region in the semiconductor layer. The graded dopant region has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer, with a gradual decrease in the doping concentration. The doped material layer is removed, and then a gate stack is formed on the semiconductor layer. Source and drain regions are formed adjacent to an active area that is in the semiconductor layer underneath the gate stack. The active area comprises at least a portion of the graded dopant region, and the source and drain regions and the active area have the same conductivity type.

    摘要翻译： 提供了一种用于制造晶体管的方法。 根据该方法，在半导体层上形成掺杂材料层，掺杂剂从掺杂材料层扩散到半导体层中，以在半导体层中形成渐变掺杂区域。 渐变掺杂区域在半导体层的顶表面附近具有更高的掺杂浓度，并且在半导体层的底表面附近具有较低的掺杂浓度，掺杂浓度逐渐降低。 去除掺杂材料层，然后在半导体层上形成栅叠层。 源极和漏极区域形成在栅极堆叠下方的半导体层中的有源区域附近。 有源区域包括渐变掺杂区域的至少一部分，源极和漏极区域以及有源区域具有相同的导电类型。

    CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES
    5.
    发明申请
    CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES 失效
    具有多个阈值电压器件的CMOS结构

    公开(公告)号：US20130062702A1

    公开(公告)日：2013-03-14

    申请号：US13227750

    申请日：2011-09-08

    申请人： Kangguo CHENG ,  Bruce B. DORIS ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI

    发明人： Kangguo CHENG ,  Bruce B. DORIS ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L29/51 ,  H01L21/28176 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606 ,  H01L29/7833

    摘要： A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.

    摘要翻译： 形成具有多个阈值电压器件的互补金属氧化物半导体（CMOS）结构的方法包括在半导体衬底上形成第一晶体管器件和第二晶体管器件。 第一晶体管器件和第二晶体管器件最初具有牺牲性虚拟栅极结构。 去除牺牲虚拟栅极结构，并且为第一晶体管器件选择性地形成一组垂直氧化物间隔物。 垂直氧化物间隔物组与第一晶体管器件的栅介质层直接接触，使得第一晶体管器件相对于第二晶体管器件具有偏移的阈值电压。

    SOI Trench Dram Structure With Backside Strap
    6.
    发明申请
    SOI Trench Dram Structure With Backside Strap 审中-公开

    公开(公告)号：US20120302020A1

    公开(公告)日：2012-11-29

    申请号：US13568580

    申请日：2012-08-07

    申请人： Bruce B. DORIS ,  Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Ghavam G. SHAHIDI

    发明人： Bruce B. DORIS ,  Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Ghavam G. SHAHIDI

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

    摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.