-
公开(公告)号:US20130270638A1
公开(公告)日:2013-10-17
申请号:US13445959
申请日:2012-04-13
申请人: Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Raghavasimhan Sreenivasan
发明人: Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Raghavasimhan Sreenivasan
IPC分类号: H01L29/78 , H01L21/336
CPC分类号: H01L29/785 , H01L29/165 , H01L29/66795 , H01L29/7848
摘要: A semiconductor structure includes an epitaxial insulator layer located on a substrate. A fin structure is located on the epitaxial insulator layer, where at least one epitaxial source-drain region having an embedded stressor is located on the epitaxial insulator layer and abuts at least one sidewall associated with the fin structure. The epitaxial source-drain region having the embedded stressor provides stress along the fin structure such that the provided stress is based on a lattice mismatch between the epitaxial source-drain region, and both the epitaxial insulator layer and the one side-wall associated with the fin structure.
摘要翻译: 半导体结构包括位于衬底上的外延绝缘体层。 翅片结构位于外延绝缘体层上,其中具有嵌入的应力源的至少一个外延源极 - 漏极区域位于外延绝缘体层上并邻接与翅片结构相关联的至少一个侧壁。 具有嵌入的应力源的外延源极 - 漏极区域沿着鳍状结构提供应力,使得所提供的应力基于外延源极 - 漏极区域和外延绝缘体层与与该外部源极 - 漏极区域相关联的一个侧壁之间的晶格失配 翅片结构。
-
公开(公告)号:US09041116B2
公开(公告)日:2015-05-26
申请号:US13478154
申请日:2012-05-23
申请人: Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人: Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号: H01L27/092 , H01L27/12 , H01L21/8238
CPC分类号: H01L21/823835 , H01L21/823842
摘要: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
-
公开(公告)号:US08923666B2
公开(公告)日:2014-12-30
申请号:US13472674
申请日:2012-05-16
摘要: Embodiments of the present invention provide an electrically controlled optical fuse. The optical fuse is activated electronically instead of by the light source itself. An applied voltage causes the fuse temperature to rise, which induces a transformation of a phase changing material from transparent to opaque. A gettering layer absorbs excess atoms released during the transformation.
摘要翻译: 本发明的实施例提供一种电控光熔丝。 光学保险丝以电子方式激活而不是由光源本身激活。 施加的电压导致熔丝温度升高,这导致相变材料从透明变为不透明。 吸收层吸收在转化期间释放的多余原子。
-
公开(公告)号:US20140070414A1
公开(公告)日:2014-03-13
申请号:US13608211
申请日:2012-09-10
IPC分类号: H01L21/283 , H01L29/49
CPC分类号: H01L21/823456 , H01L29/66545
摘要: Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.
摘要翻译: 公开了具有不同栅极长度和制造方法的栅极结构。 该方法包括使用掩模的图案形成具有第一临界尺寸的第一栅极结构。 该方法还包括使用掩模的图案形成具有与第一栅极结构的第一临界尺寸不同的第二临界尺寸的第二栅极结构。
-
公开(公告)号:US20140070333A1
公开(公告)日:2014-03-13
申请号:US13613436
申请日:2012-09-13
IPC分类号: H01L21/336 , H01L29/78
CPC分类号: H01L29/42364 , H01L21/28079 , H01L29/495 , H01L29/511 , H01L29/66545 , H01L29/78 , H01L29/7833
摘要: A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the gate conductor is recessed relative to the interlevel dielectric layer. A multi-layered cap is formed a recessed surface of the gate structure, wherein at least one layer of the multi-layered cap includes a high-k dielectric material and is present on a sidewall of the gate sidewall spacer at an upper surface of the functional gate structure. Via openings are etched through the interlevel dielectric layer selectively to at least the high-k dielectric material of the multi-layered cap, wherein at least the high-k dielectric material protects a sidewall of the gate conductor.
摘要翻译: 一种形成半导体器件的方法,包括在半导体衬底的沟道部分上提供功能栅极结构。 栅极侧壁间隔物与功能栅极结构相邻,并且层间介质层邻近栅极侧壁间隔物存在。 栅极导体的上表面相对于层间电介质层凹陷。 多层盖形成了栅极结构的凹陷表面,其中多层盖的至少一层包括高k电介质材料,并且存在于栅侧壁间隔物的侧壁上 功能门结构。 通过开孔蚀刻穿过层间电介质层至少至多层多层盖的高k电介质材料,其中至少高k绝缘材料保护栅极导体的侧壁。
-
公开(公告)号:US20140035141A1
公开(公告)日:2014-02-06
申请号:US13562341
申请日:2012-07-31
IPC分类号: H01L23/48 , H01L21/768
CPC分类号: H01L21/76834 , H01L21/28518 , H01L21/76823 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要: A method of fabricating a semiconductor structure having a borderless contact, the method including providing a first semiconductor device adjacent to a second semiconductor device, the first and second semiconductor devices being formed on a semiconductor substrate, depositing a non-conductive liner on top of the semiconductor substrate and the first and second semiconductor devices, depositing a contact level dielectric layer on top of the non-conductive liner, etching a contact hole in the contact-level dielectric between the first semiconductor device and the second semiconductor device, and selective to the non-conductive liner, converting a portion of the non-conductive liner exposed in the contact hole into a conductive liner; and forming a metal contact in the contact hole.
摘要翻译: 一种制造具有无边界接触的半导体结构的方法,所述方法包括提供与第二半导体器件相邻的第一半导体器件,所述第一和第二半导体器件形成在半导体衬底上,在非导电衬底的顶部上沉积非导电衬垫 半导体衬底和第一和第二半导体器件,在非导电衬垫的顶部上沉积接触电介质层,蚀刻第一半导体器件和第二半导体器件之间的接触电平电介质中的接触孔,并且对 将非接触孔中暴露的非导电衬垫的一部分转换成导电衬垫; 并在接触孔中形成金属接触。
-
公开(公告)号:US20130207226A1
公开(公告)日:2013-08-15
申请号:US13371665
申请日:2012-02-13
申请人: Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Raghavasimhan Sreenivasan
发明人: Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Raghavasimhan Sreenivasan
IPC分类号: H01L29/06 , H01L21/762
CPC分类号: H01L21/762 , H01L29/1079 , H01L29/772 , H01L29/78603
摘要: A method for isolating semiconductor devices is described wherein an epitaxial insulating layer is grown on a semiconductor substrate. The epitaxial insulating layer is etched to form a recessed region within the layer. An epitaxial semiconductor material is grown with the recessed region to form a semiconductor device region separated from other potential device regions by non-recessed portions of the epitaxial insulating layer.
摘要翻译: 其中描述了半导体器件的隔离方法,其中在半导体衬底上生长外延绝缘层。 外延绝缘层被蚀刻以在层内形成凹陷区域。 外延半导体材料与凹陷区域一起生长以形成通过外延绝缘层的非凹陷部分与其它电位器件区域分离的半导体器件区域。
-
公开(公告)号:US09034703B2
公开(公告)日:2015-05-19
申请号:US13613436
申请日:2012-09-13
CPC分类号: H01L29/42364 , H01L21/28079 , H01L29/495 , H01L29/511 , H01L29/66545 , H01L29/78 , H01L29/7833
摘要: A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the gate conductor is recessed relative to the interlevel dielectric layer. A multi-layered cap is formed a recessed surface of the gate structure, wherein at least one layer of the multi-layered cap includes a high-k dielectric material and is present on a sidewall of the gate sidewall spacer at an upper surface of the functional gate structure. Via openings are etched through the interlevel dielectric layer selectively to at least the high-k dielectric material of the multi-layered cap, wherein at least the high-k dielectric material protects a sidewall of the gate conductor.
摘要翻译: 一种形成半导体器件的方法,包括在半导体衬底的沟道部分上提供功能栅极结构。 栅极侧壁间隔物与功能栅极结构相邻,并且层间介质层邻近栅极侧壁间隔物存在。 栅极导体的上表面相对于层间电介质层凹陷。 多层盖形成了栅极结构的凹陷表面,其中多层盖的至少一层包括高k电介质材料,并且存在于栅侧壁间隔物的侧壁上 功能门结构。 通过开孔蚀刻穿过层间电介质层至少至多层多层盖的高k电介质材料,其中至少高k绝缘材料保护栅极导体的侧壁。
-
公开(公告)号:US08802565B2
公开(公告)日:2014-08-12
申请号:US13608211
申请日:2012-09-10
IPC分类号: H01L21/302
CPC分类号: H01L21/823456 , H01L29/66545
摘要: Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.
-
公开(公告)号:US20130334603A1
公开(公告)日:2013-12-19
申请号:US13525650
申请日:2012-06-18
IPC分类号: H01L29/78 , H01L21/302
CPC分类号: H01L21/76283 , H01L21/76232 , H01L29/66772 , H01L29/78654
摘要: A method including etching a shallow trench laterally surrounding a portion of a semiconductor substrate, the semiconductor substrate comprising a semiconductor-on-insulator SOI layer, a pad oxide layer, and a pad nitride layer, depositing a first nitride liner, a dielectric liner, and a second nitride liner in the shallow trench, wherein the dielectric liner is located between the first and the second nitride liner, and filling the shallow trench with a shallow trench fill portion.
摘要翻译: 一种方法,包括蚀刻横向围绕半导体衬底的一部分的浅沟槽,所述半导体衬底包括绝缘体上半导体SOI层,衬垫氧化物层和衬垫氮化物层,沉积第一氮化物衬垫,介电衬垫, 以及浅沟槽中的第二氮化物衬垫,其中所述电介质衬垫位于所述第一和第二氮化物衬垫之间,并且用浅沟槽填充部分填充所述浅沟槽。
-
-
-
-
-
-
-
-
-