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公开(公告)号：US20140008729A1
公开(公告)日：2014-01-09
申请号：US13615016
申请日：2012-09-13
IPC分类号： H01L21/336 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： A structure includes a tensilely strained nFET region including a strained silicon layer of a silicon on insulator wafer. A relaxed nFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer. A compressively strained pFET region includes a SiGe layer which was converted from a tensilely strained silicon layer of the silicon on insulator wafer. A relaxed pFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer.
摘要翻译： 一种结构包括包括绝缘体硅晶片的应变硅层的拉伸应变nFET区域。 松弛的nFET区域包括离子注入硅和绝缘体硅晶片的拉伸应变硅层的离子注入二氧化硅界面层之一。 压缩应变pFET区域包括从绝缘体硅晶片的拉伸应变硅层转换的SiGe层。 松弛的pFET区域包括离子注入硅和绝缘硅晶片上的拉伸应变硅层的离子注入二氧化硅界面层之一。
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公开(公告)号：US20140011328A1
公开(公告)日：2014-01-09
申请号：US13544093
申请日：2012-07-09
IPC分类号： H01L21/84 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： A method for fabricating field effect transistors patterns a strained silicon layer formed on a dielectric layer of a substrate into at least one NFET region including at least a first portion of the strained silicon layer. The strained silicon layer is further patterned into at least one PFET region including at least a second portion of the strained silicon layer. A masking layer is formed over the first portion of the strained silicon layer. After the masking layer has been formed, the second strained silicon layer is transformed into a relaxed silicon layer. The relaxed silicon layer is transformed into a strained silicon germanium layer.
摘要翻译： 用于制造场效应晶体管的方法将形成在衬底的电介质层上的应变硅层图案化成至少一个包括应变硅层的第一部分的NFET区域。 将应变硅层进一步图案化成至少一个包括应变硅层的至少第二部分的PFET区域。 在应变硅层的第一部分上形成掩模层。 在形成掩模层之后，将第二应变硅层转变成松弛的硅层。 松弛的硅层被转变成应变硅锗层。
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公开(公告)号：US20120216158A1
公开(公告)日：2012-08-23
申请号：US13457932
申请日：2012-04-27
申请人： Stephen W. BEDELL , Kangguo CHENG , Bruce B. DORIS , Ali KHAKIFIROOZ , Pranita KULKARNI , Katherine L. SAENGER
发明人： Stephen W. BEDELL , Kangguo CHENG , Bruce B. DORIS , Ali KHAKIFIROOZ , Pranita KULKARNI , Katherine L. SAENGER
CPC分类号： H01L21/84 , H01L21/823807
摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.
摘要翻译： 应变Si和应变SiGe绝缘体器件，制造方法和设计结构。 该方法包括在绝缘体上硅晶片上生长SiGe层。 该方法还包括将SiGe层图案化成PFET和NFET区域，使得PFET和NFET区域中的SiGe层中的应变被放宽。 该方法还包括通过离子注入直接在SiGe层下面的Si层的至少一部分而非晶化。 该方法还包括进行热退火以使Si层重结晶，使得晶格常数与弛豫SiGe的晶格常数相匹配，从而在NFET区域上产生拉伸应变。 该方法还包括从NFET区域去除SiGe层。 该方法还包括执行Ge工艺以将PFET区域中的Si层转换为压缩应变的SiGe。
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4.发明申请公开(公告)号：US20130178021A1
公开(公告)日：2013-07-11
申请号：US13614908
申请日：2012-09-13
申请人： Kangguo CHENG , Bruce DORIS , Ali KHAKIFIROOZ , Ghavam G. SHAHIDI
发明人： Kangguo CHENG , Bruce DORIS , Ali KHAKIFIROOZ , Ghavam G. SHAHIDI
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/32053 , H01L21/823814 , H01L27/0629 , H01L27/1203 , H01L29/41783
摘要： A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.
摘要翻译： 隔离第一半导体层中的第一半导体层和电容器区域的晶体管区域。 在晶体管区域的第一半导体层上形成虚拟栅极结构。 在第一半导体层上形成第二半导体层。 第二半导体层的第一和第二部分位于晶体管区域中，第二半导体层的第三部分位于电容器区域中。 第一，第二和第三硅化物区分别形成在第二半导体层的第一，第二和第三部分上。 在形成电介质层之后，去除伪栅极结构形成第一腔。 位于第三硅化物区域上方的电介质层的至少一部分被去除，形成第二腔。 在第一腔中形成栅极电介质，在第二腔中形成电容器电介质。
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5.发明申请公开(公告)号：US20130175596A1
公开(公告)日：2013-07-11
申请号：US13345266
申请日：2012-01-06
申请人： Kangguo CHENG , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo CHENG , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L21/84 , H01L21/32053 , H01L21/823814 , H01L27/0629 , H01L27/1203 , H01L29/41783
摘要： An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.
摘要翻译： 集成电路包括晶体管和电容器。 晶体管包括位于第一半导体层上的第一半导体层和栅极堆叠。 栅堆叠包括金属层和第一高k电介质层。 栅极间隔物位于栅极叠层的侧壁上。 第一高k电介质层位于第一半导体层和金属层之间以及栅间隔物和金属层的侧壁之间。 第一硅化物区域位于第一源极/漏极区域上。 第二硅化物区域位于第二源极/漏极区域上。 电容器包括第一端子，其包括位于第二半导体的一部分上的第三硅化物区域。 第二高k电介质层位于硅化物区域上。 第二端子包括位于第二高k电介质层上的金属层。
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6.发明申请RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER 有权从应力衬里增强应变耦合的提高源/排水结构公开(公告)号：US20120299103A1
公开(公告)日：2012-11-29
申请号：US13570833
申请日：2012-08-09
IPC分类号： H01L29/06
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译： 提供一种晶体管，其包括衬底上方的掩埋氧化物层。 硅层在掩埋氧化物层之上。 栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。 氮化物衬垫与栅堆叠相邻。 氧化物衬垫与氮化物衬垫相邻。 一组具有包括硅层的一部分的部分的凸起的源/漏区。 所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。
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7.发明申请RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER 有权从应力衬里增强应变耦合的提高源/排水结构公开(公告)号：US20130011975A1
公开(公告)日：2013-01-10
申请号：US13614572
申请日：2012-09-13
IPC分类号： H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack comprises a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A first nitride layer is formed on the silicon layer and the gate stack. An oxide layer is formed on the first nitride layer. A second nitride layer is formed on the oxide layer. The first nitride layer and the oxide layer are etched so as to form a nitride liner and an oxide liner adjacent to the gate stack. The second nitride layer is etched so as to form a first nitride spacer adjacent to the oxide liner. A faceted raised source/drain region is epitaxially formed adjacent to the nitride liner, the oxide liner, and first nitride spacer. Ions are implanted into the faceted raised source/drain region using the first nitride spacer.
摘要翻译： 栅极堆叠形成在掩埋氧化物层上方的硅层上。 栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。 在硅层和栅叠层上形成第一氮化物层。 在第一氮化物层上形成氧化物层。 在氧化物层上形成第二氮化物层。 蚀刻第一氮化物层和氧化物层，以便形成氮化物衬垫和邻近栅叠层的氧化物衬垫。 蚀刻第二氮化物层以形成邻近氧化物衬垫的第一氮化物间隔物。 与氮化物衬垫，氧化物衬垫和第一氮化物间隔物相邻地外延形成刻面隆起的源极/漏极区。 使用第一氮化物间隔物将离子植入到刻面隆起的源极/漏极区域中。
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8.发明申请METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN 审中-公开用于制作具有残留通道和放大源/漏极的晶体管的方法公开(公告)号：US20130178022A1
公开(公告)日：2013-07-11
申请号：US13618186
申请日：2012-09-14
申请人： Kangguo CHENG , Ali KHAKIFIROOZ , Sivananda KANAKASABAPATHY , Pranita KULKARNI , Balasubramanian S. HARAN
发明人： Kangguo CHENG , Ali KHAKIFIROOZ , Sivananda KANAKASABAPATHY , Pranita KULKARNI , Balasubramanian S. HARAN
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/7848 , H01L29/785
摘要： A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer.
摘要翻译： 提供了一种用于制造晶体管的方法。 根据该方法，在第一半导体层上形成第二半导体层，在第二半导体层上形成虚拟栅极结构。 栅极间隔件形成在虚拟栅极结构的侧壁上，并且去除虚拟栅极结构以形成空腔。 除去腔下方的第二半导体层。 栅电介质形成在第一半导体层的第一部分上并且邻近第二半导体层的侧壁和栅极间隔物的侧壁。 栅极导体形成在栅极电介质的第一部分上并邻接栅极电介质的第二部分。 凸起的源/漏区形成在第二半导体层中，其中至少部分凸起的源极/漏极区在栅极间隔物之下。
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公开(公告)号：US20120313168A1
公开(公告)日：2012-12-13
申请号：US13155878
申请日：2011-06-08
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.
摘要翻译： 极薄的绝缘体上硅晶体管包括在衬底上方的掩埋氧化物层。 掩埋氧化物层例如具有小于50nm的厚度。 硅层在掩埋氧化物层之上。 硅层上的栅极叠层包括至少形成在硅层上的栅极电介质和形成在栅极电介质上的栅极导体。 栅极间隔物在硅层上具有第一部分，第二部分邻近栅极堆叠。 第一升高的源极/漏极区域和第二升高的源极/漏极区域各自具有包括硅层的一部分的第一部分和与栅极间隔物相邻的第二部分。 至少部分地在衬底内形成至少一个嵌入式应力器，其在硅层中形成的硅沟道区域上施加预定的应力。
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公开(公告)号：US20130078777A1
公开(公告)日：2013-03-28
申请号：US13618054
申请日：2012-09-14
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/1203 , H01L29/78654 , H01L29/78696
摘要： A method is provided for fabricating a transistor. According to the method, a doped material layer is formed on a semiconductor layer, and dopant is diffused from the doped material layer into the semiconductor layer to form a graded dopant region in the semiconductor layer. The graded dopant region has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer, with a gradual decrease in the doping concentration. The doped material layer is removed, and then a gate stack is formed on the semiconductor layer. Source and drain regions are formed adjacent to an active area that is in the semiconductor layer underneath the gate stack. The active area comprises at least a portion of the graded dopant region, and the source and drain regions and the active area have the same conductivity type.
摘要翻译： 提供了一种用于制造晶体管的方法。 根据该方法，在半导体层上形成掺杂材料层，掺杂剂从掺杂材料层扩散到半导体层中，以在半导体层中形成渐变掺杂区域。 渐变掺杂区域在半导体层的顶表面附近具有更高的掺杂浓度，并且在半导体层的底表面附近具有较低的掺杂浓度，掺杂浓度逐渐降低。 去除掺杂材料层，然后在半导体层上形成栅叠层。 源极和漏极区域形成在栅极堆叠下方的半导体层中的有源区域附近。 有源区域包括渐变掺杂区域的至少一部分，源极和漏极区域以及有源区域具有相同的导电类型。
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