公开(公告)号：US07968459B2

公开(公告)日：2011-06-28

申请号：US12128040

申请日：2008-05-28

申请人： Stephen W. Bedell ,  Joel P. DeSouza ,  Zhibin Ren ,  Alexander Reznicek ,  Devandra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi

发明人： Stephen W. Bedell ,  Joel P. DeSouza ,  Zhibin Ren ,  Alexander Reznicek ,  Devandra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi

IPC分类号： H01L21/44

CPC分类号： H01L29/66628 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

摘要翻译： 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源/漏（S / D）区域的潜在问题）的方法， 以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

公开(公告)号：US20080258220A1

公开(公告)日：2008-10-23

申请号：US12128040

申请日：2008-05-28

申请人： Stephen W. Bedell ,  Joel P. De Souza ,  Zhibin Ren ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi

发明人： Stephen W. Bedell ,  Joel P. De Souza ,  Zhibin Ren ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi

IPC分类号： H01L27/12 ,  H01L21/8234

CPC分类号： H01L29/66628 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

摘要翻译： 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源极/漏极（S / D）区域的潜在问题）的方法， 以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

公开(公告)号：US20090134460A1

公开(公告)日：2009-05-28

申请号：US12363239

申请日：2009-01-30

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/00 ,  H01L21/71

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US07485539B2

公开(公告)日：2009-02-03

申请号：US11332564

申请日：2006-01-13

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/76

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US20080277690A1

公开(公告)日：2008-11-13

申请号：US12176624

申请日：2008-07-21

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/76259 ,  Y10S438/967

摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

摘要翻译： 提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。 该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。 该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。 根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

公开(公告)号：US07172930B2

公开(公告)日：2007-02-06

申请号：US10883887

申请日：2004-07-02

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/36

CPC分类号： H01L21/76259 ,  Y10S438/967

摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

摘要翻译： 提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。 该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。 该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。 根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

公开(公告)号：US07897444B2

公开(公告)日：2011-03-01

申请号：US12363239

申请日：2009-01-30

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/84

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US07592671B2

公开(公告)日：2009-09-22

申请号：US11620663

申请日：2007-01-06

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L29/94

CPC分类号： H01L21/76259 ,  Y10S438/967

摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

摘要翻译： 提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。 该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。 该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。 根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

公开(公告)号：US20070257315A1

公开(公告)日：2007-11-08

申请号：US11417846

申请日：2006-05-04

申请人： Stephen Bedell ,  Joel De Souza ,  Zhibin Ren ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Joel De Souza ,  Zhibin Ren ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger ,  Ghavam Shahidi

IPC分类号： H01L21/8234

CPC分类号： H01L21/26513 ,  H01L21/2658 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

摘要翻译： 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源极/漏极（S / D）区域的潜在问题）的方法， 以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

公开(公告)号：US20100006985A1

公开(公告)日：2010-01-14

申请号：US12170459

申请日：2008-07-10

申请人： Joel P. DeSouza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra Sadana

发明人： Joel P. DeSouza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra Sadana

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L21/76245

摘要： A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.

摘要翻译： 提供了一种制造绝缘体上硅衬底的方法。 这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。 随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。 上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。 然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层 从底层半导体区域。 可以在非高p型掺杂外延层同时退火的同时执行这种处理。