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    Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator
    2.
    发明授权
    Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator 有权
    通过在绝缘体上半导体中加入和除去原子的绝缘体上的应变半导体

    公开(公告)号：US08361889B2

    公开(公告)日：2013-01-29

    申请号：US12830626

    申请日：2010-07-06

    申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/20

    CPC分类号： H01L29/1054 ,  H01L29/7833

    摘要： A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate.

    摘要翻译： 提供了一种形成不包括晶片接合的应变绝缘体上半导体（SSOI）衬底的方法。 在本公开中，在绝缘体上硅（SOI）衬底的上表面上形成松弛和掺杂的硅层。 在一个实施例中，松弛和掺杂硅层内的掺杂剂具有小于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数小于硅的原子尺寸， 下层SOI层的平面晶格参数。 在另一实施例中，松弛和掺杂硅层内的掺杂剂具有大于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数大于硅原子尺寸， 下层SOI层的平面晶格参数。 在SOI衬底上形成松弛和掺杂的硅层之后，从该层去除松弛和掺杂硅层内的掺杂剂，将松散和掺杂的硅层转化成形成在上层的应变（压缩或拉伸）硅层 SOI衬底的表面。

    STRAIN-PRESERVING ION IMPLANTATION METHODS
    4.
    发明申请
    STRAIN-PRESERVING ION IMPLANTATION METHODS 失效
    应变保留离子植入方法

    公开(公告)号：US20110230030A1

    公开(公告)日：2011-09-22

    申请号：US12724608

    申请日：2010-03-16

    申请人： Joel P. de Souza ,  Masafumi Hamaguchi ,  Ahmet S. Ozcan ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Donald R. Wall

    发明人： Joel P. de Souza ,  Masafumi Hamaguchi ,  Ahmet S. Ozcan ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Donald R. Wall

    IPC分类号： H01L21/336

    CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.

    摘要翻译： 具有与半导体衬底的矩阵不同的组成的嵌入式外延半导体部分与半导体衬底的矩阵形成晶格失配和外延对准。 随后离子注入步骤的温度根据离子注入工艺的非晶化或非非晶化性质进行操作。 对于非非晶化离子注入工艺，离子注入处理步骤在升高的温度，即大于标称室温范围的温度下进行。 对于非晶化离子注入工艺，离子注入处理步骤在标称室温范围或低于标称室温范围的温度下进行。 通过操纵离子注入的温度，使应变半导体合金材料中的应变损失最小化。

    Dual SIMOX hybrid orientation technology (HOT) substrates
    7.
    发明授权
    Dual SIMOX hybrid orientation technology (HOT) substrates 失效
    双SIMOX混合取向技术（HOT）底物

    公开(公告)号：US07253034B2

    公开(公告)日：2007-08-07

    申请号：US10902557

    申请日：2004-07-29

    申请人： Kevin K. Chan ,  Joel P. de Souza ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

    发明人： Kevin K. Chan ,  Joel P. de Souza ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

    IPC分类号： H01L21/70 ,  H01L21/762

    CPC分类号： H01L21/84 ,  H01L21/76243 ,  H01L21/76267 ,  H01L27/1203 ,  H01L27/1207

    摘要： This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orientations providing optimal performance. The method includes the steps of selecting a substrate having a base semiconductor layer having a first crystallographic orientation separated by a thin insulating layer from a top semiconductor layer having a second crystallographic orientation; replacing the top semiconductor layer in selected regions with an epitaxially grown semiconductor having the first crystallographic orientation; then using an ion implantation and annealing method to (i) form a buried insulating region within the epitaxially grown semiconductor material, and (ii) thicken the insulating layer underlying the top semiconductor layer, thereby forming a hybrid orientation substrate in which the two semiconductor materials with different crystallographic orientations have substantially the same thickness and are both disposed on a common buried insulator layer. In a variation of this method, an ion implantation and annealing method is instead used to extend an auxiliary buried insulator layer (initially underlying the base semiconductor layer) upwards (i) into the epitaxially grown semiconductor, and (ii) up to the insulating layer underlying the top semiconductor layer.

    摘要翻译： 本发明提供了通过注入氧（SIMOX）分离方法，用于形成具有不同晶体取向的平面杂化取向绝缘体上半导体（SOI）衬底，从而使得可以以提供最佳性能的晶体取向来制造器件。 该方法包括以下步骤：从具有第二晶体取向的顶部半导体层选择具有由薄绝缘层分离的第一晶体取向的基底半导体层的衬底; 用具有第一晶体取向的外延生长的半导体代替选定区域中的顶部半导体层; 然后使用离子注入和退火方法来（i）在外延生长的半导体材料内形成掩埋绝缘区，并且（ii）加厚顶部半导体层下面的绝缘层，从而形成混合取向衬底，其中两个半导体材料 具有不同的晶体取向具有基本上相同的厚度并且均设置在公共掩埋绝缘体层上。 在该方法的变型中，替代地使用离子注入和退火方法将辅助掩埋绝缘体层（最初在基底半导体层下面）向上（i）延伸到外延生长的半导体中，以及（ii）直到绝缘层 在顶部半导体层下面。

    Defect induced buried oxide (DIBOX) for throughput SOI
    8.
    发明授权
    Defect induced buried oxide (DIBOX) for throughput SOI 失效
    缺陷诱导埋氧（DIBOX）用于吞吐量SOI

    公开(公告)号：US06259137B1

    公开(公告)日：2001-07-10

    申请号：US09264973

    申请日：1999-03-09

    申请人： Devendra Kumar Sadana ,  Joel P. de Souza

    发明人： Devendra Kumar Sadana ,  Joel P. de Souza

    IPC分类号： H01L2900

    CPC分类号： H01L21/26533 ,  H01L21/2654 ,  H01L21/76243

    摘要： A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing a first low energy implantation step to create a stable defect region; a second low energy implantation step to create an amorphous layer adjacent to the stable defect region; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising said semiconductor substrate having said DIBOX is also provided herein.

    摘要翻译： 利用第一低能量注入步骤在半导体衬底中制造缺陷诱导的掩埋氧化物（DIBOX）区域以产生稳定的缺陷区域的方法; 第二低能量注入步骤，以产生邻近所述稳定缺陷区域的非晶层; 提供氧化和任选的退火。 也提供了包含具有所述DIBOX的所述半导体衬底的绝缘体上硅（SOI）材料。