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公开(公告)号：US06502150B1
公开(公告)日：2002-12-31
申请号：US09205649
申请日：1998-12-03
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： A computer system that includes at least two host agents is provided. The computer system further includes a chipset that includes a resource to be shared by the at least two host agents. The chipset is coupled to the-at least two host agents. The chipset prevents a first host agent, that occupies the shared resource to access the shared resource until a second host agent, has made progress in accessing said shared resource.
摘要翻译： 提供了包括至少两个主机代理的计算机系统。 计算机系统还包括芯片组，其包括要由至少两个主机代理共享的资源。 芯片组耦合到至少两个主机代理。 芯片组防止占用共享资源的第一主机代理访问共享资源，直到第二个主机代理在访问所述共享资源时取得进展。
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2.发明授权公开(公告)号：US06314497B1
公开(公告)日：2001-11-06
申请号：US09205646
申请日：1998-12-03
IPC分类号： G06F1212
CPC分类号： G06F12/0835 , G06F12/0804
摘要： According to one embodiment, a computer system is disclosed. The computer system includes a processor, a memory, an inverting device, a storage device coupled to the inverting device and a device coupled to the storage device. The device receives byte enable information and inverted information and provides inverted byte enable information to the memory upon a write back operation to the memory.
摘要翻译： 根据一个实施例，公开了一种计算机系统。 计算机系统包括处理器，存储器，反相装置，耦合到反相装置的存储装置和耦合到存储装置的装置。 该设备接收字节使能信息和反相信息，并且在对存储器的回写操作时向存储器提供反转字节使能信息。
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公开(公告)号：US06385703B1
公开(公告)日：2002-05-07
申请号：US09205647
申请日：1998-12-03
IPC分类号： G06F1314
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A computer system that includes a host processor (HP), a system memory (SM), and a host bridge coupled to the HP and SM is provided. The host bridge asserts a first read request to the SM and, prior to availability of snoop results in connection with the first read request, the host bridge asserts a following second read request to the SM.
摘要翻译： 提供了一种包括主机处理器（HP），系统存储器（SM）和耦合到HP和SM的主机桥的计算机系统。 主桥向SM发出第一次读取请求，并且在与第一个读取请求相关的侦听结果的可用性之前，主桥向SM发出以下第二个读取请求。
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公开(公告)号：US6157397A
公开(公告)日：2000-12-05
申请号：US50381
申请日：1998-03-30
CPC分类号： G06F3/14
摘要： A method for graphics device read and processor write coherency receives a write request from a processor to write data to a storage element for a component to read and flushes the data to the storage element prior to the component reading the address associated with the data in the storage element.
摘要翻译： 用于图形设备读取和处理器写入一致性的方法从处理器接收写入请求，以将数据写入存储元件，以便组件在组件读取与数据相关联的地址之前将数据读取和刷新到存储元件 存储元件
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公开(公告)号：US20080133952A1
公开(公告)日：2008-06-05
申请号：US11633183
申请日：2006-12-04
申请人： Chai Huat Gan , Darren Abramson , Zohar Bogin
发明人： Chai Huat Gan , Darren Abramson , Zohar Bogin
CPC分类号： G06F1/3225
摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.
摘要翻译： 对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。 缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。 如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是 服务。 在此期间，系统DRAM可能会开始刷新。 一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。 描述和要求保护其他实施例。
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6.发明授权公开(公告)号：US07181605B2
公开(公告)日：2007-02-20
申请号：US10693226
申请日：2003-10-24
申请人： Zohar Bogin , Surya Kareenahalli , Anoop Mukker , David Sastry , Tuong Trieu
发明人： Zohar Bogin , Surya Kareenahalli , Anoop Mukker , David Sastry , Tuong Trieu
IPC分类号： G06F9/00
CPC分类号： G06F1/24
摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.
摘要翻译： 已经公开了响应于系统热复位来确定地关闭存储器件的方法。 该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式 控制器，其在存储器件初始化之后耦合到存储器件。 描述和要求保护其他实施例。
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公开(公告)号：US07082480B2
公开(公告)日：2006-07-25
申请号：US10674944
申请日：2003-09-29
申请人： Zohar Bogin , Serafin E. Garcia
发明人： Zohar Bogin , Serafin E. Garcia
IPC分类号： G06F3/00
CPC分类号： G06F13/24 , G06F13/385
摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.
摘要翻译： 在具有调度器和多个下行命令队列的计算机系统中防止死锁和活动锁的技术的组合。 在一个实施例中，需要在所有受影响的下游命令队列中同时可用空间的广播事务变成延迟的事务，使得命令队列被保留，并且重试其他事务直到广播事务完成。 在另一个实施例中，如果事务在预定时间内未完成，则使用拯救计时器推迟事务。 在另一个实施例中，如果存在小于可用于该事务的预定量的下游缓冲区空间，则潜在地解决由可编程属性映射控制的存储空间的锁定事务被处理为延迟事务。
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公开(公告)号：US06983339B1
公开(公告)日：2006-01-03
申请号：US09675801
申请日：2000-09-29
IPC分类号： G06F1/00
CPC分类号： G06F13/24
摘要： A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.
摘要翻译： 一种用于将APIC中断传送到处理器和处理器之间的方法和装置，作为FSB事务。 由PCI设备生成的中断和硬件信号被转换为上游存储器写入中断，并进一步转换为由处理器接收的FSB中断事务。 标记为最低优先级可重定向的中断根据任务优先级信息重定向。 提供对XTPR事务的支持以更新XTPR寄存器。 提供XTPR更新事务和重定向中断的优先顺序。
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公开(公告)号：US20050195202A1
公开(公告)日：2005-09-08
申请号：US10796686
申请日：2004-03-08
申请人： David Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
发明人： David Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
CPC分类号： G06F13/1684
摘要： Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.
摘要翻译： 本发明的实施例涉及使用双通道存储器件的第一通道访问第一对相邻数据块; 并且使用所述存储器件的第二通道同时访问第二对相邻数据块，所述第二对与所述第一对间隔开预定间隔。
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公开(公告)号：US20050143843A1
公开(公告)日：2005-06-30
申请号：US10723132
申请日：2003-11-25
CPC分类号： G10L19/167
摘要： Machine-readable media, methods, and apparatus are described to pace commands to codecs. Some embodiments comprise an audio controller that transfers frames to codecs and places commands in the frames at a pace dictated by a command pacer.
摘要翻译： 描述了机器可读介质，方法和装置，以将命令调整到编解码器。 一些实施例包括音频控制器，该音频控制器将帧传送到编解码器，并以由命令起搏器指示的速度将命令放置在帧中。
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