Method and system for supply chain product and process development collaboration
    1.
    发明授权
    Method and system for supply chain product and process development collaboration 有权
    供应链产品和过程开发协作的方法和系统

    公开(公告)号:US07747572B2

    公开(公告)日:2010-06-29

    申请号:US09802398

    申请日:2001-03-09

    IPC分类号: G06F17/30

    CPC分类号: G06Q10/06 G06Q10/087

    摘要: A method and system for supply chain product and process development collaboration. The supply chain is comprised of at least one project, each project having a part (or family of parts), a supplier of the part, and a customer. The system may include a data storage and retrieval device operably connected to a processor. The system's functions include collaboration tools and security based on the users' project roles. The method uses a methodology that ensures certain requirements are met prior to satisfying the methodology. The system and method of the present invention ensures that current, applicable methodologies are applied to a specific part and allows for collaboration between the customer and supplier during all phases of the project. Because all projects in a supply chain are present, a user can navigate throughout the supply chain. The supply chain's reporting functions permit determination of potential performance risks and the source thereof.

    摘要翻译: 供应链产品和过程开发协作的方法和系统。 供应链由至少一个项目组成,每个项目都有零件(或零件系列),零件供应商和客户。 该系统可以包括可操作地连接到处理器的数据存储和检索装置。 系统的功能包括基于用户项目角色的协作工具和安全性。 该方法使用一种确保满足方法之前满足某些要求的方法。 本发明的系统和方法确保将当前适用的方法应用于特定部分,并允许客户和供应商在项目的所有阶段之间的协作。 因为供应链中的所有项目都存在,用户可以在整个供应链中进行导航。 供应链的报告功能可以确定潜在的业绩风险及其来源。

    Compositions for use in security marking

    公开(公告)号:US10472676B2

    公开(公告)日:2019-11-12

    申请号:US13265758

    申请日:2010-04-23

    摘要: A composition comprising: a plurality of identical first synthetic nucleotide oligomers; and a plurality of identical second synthetic nucleotide oligomers which are different to the first synthetic nucleotide oligomers, wherein each of the first synthetic nucleotide oligomers comprises a first primer binding sequence of bases, a first identifier sequence of three to seven bases in length, and a second primer binding sequence of bases, the first identifier sequence being disposed between the first and second primer binding sequences, wherein each of the second synthetic nucleotide oligomers comprises a third primer binding sequence of bases, a second identifier sequence of three to seven bases in length, and a fourth primer binding sequence of bases, the second identifier sequence being disposed between the third and fourth primer binding sequences, and wherein the first identifier sequence is different to the second identifier sequence.

    UICC control over devices used to obtain service
    4.
    发明授权
    UICC control over devices used to obtain service 有权
    UICC控制用于获取服务的设备

    公开(公告)号:US08639290B2

    公开(公告)日:2014-01-28

    申请号:US12567278

    申请日:2009-09-25

    IPC分类号: H04B1/38

    CPC分类号: H04M1/67 H04M2250/14

    摘要: Devices and methods are disclosed by which a smart card or UICC that is removably insertable into a wireless terminal will only allow operation in either a specific terminal or a specific set of terminals. A mechanism to restrict the set of terminals that a UICC will operate with based upon logic embedded in a memory within the UICC. The UICC receives specific information from the wireless terminal when the terminal is turned on. If the information received satisfies a plurality of rules or conditions stored within the UICC, the UICC functions normally and the terminal may be registered with the network. If the UICC is inserted in an unsupported terminal, the UICC will refuse to function normally. This provides a deterrent against UICC theft.

    摘要翻译: 公开了可移除地插入到无线终端中的智能卡或UICC的设备和方法将仅允许在特定终端或特定终端集合中进行操作。 一种基于嵌入在UICC内的存储器中的逻辑来限制UICC将运行的终端集的机制。 当终端打开时,UICC从无线终端接收特定信息。 如果接收到的信息满足存储在UICC内的多个规则或条件,则UICC正常工作,终端可以向网络注册。 如果UICC插入不支持的终端,则UICC将拒绝正常运行。 这为UICC盗窃提供了威慑力。

    METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER
    5.
    发明申请
    METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER 审中-公开
    高电压缓冲器的方法,器件和系统

    公开(公告)号:US20110298494A1

    公开(公告)日:2011-12-08

    申请号:US13210914

    申请日:2011-08-16

    IPC分类号: H03K19/094

    CPC分类号: H03K19/01721

    摘要: Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry that provide voltages to thin-gate dielectric transistors. One such buffer may include a primary pull-up pre-driver operably coupled to a primary pull-up transistor; a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor; a primary pull-down pre-driver operably coupled to a primary pull-down transistor; and a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor. The pre-drivers may provide a sufficiently low voltage to a gate of a transistor operably coupled thereto so as to sustain a gate dielectric integrity of the transistor, wherein at least one of the primary pull-up pre-driver, the secondary pull-up pre-driver, primary pull-down pre-driver, and the secondary pull-down pre-driver is configured to provide a voltage greater than or equal to a ground voltage and less than or equal to a supply voltage.

    摘要翻译: 公开了方法,装置和系统,包括用于具有向薄栅极介质晶体管提供电压的预驱动器电路的缓冲器。 一个这样的缓冲器可以包括可操作地耦合到初级上拉晶体管的初级上拉预驱动器; 可操作地耦合到次级上拉晶体管的次级上拉预驱动器; 可操作地耦合到初级下拉晶体管的主下拉预驱动器; 以及可操作地耦合到次级下拉晶体管的次级下拉预驱动器。 预驱动器可以向可操作地耦合到其的晶体管的栅极提供足够低的电压,以便维持晶体管的栅极电介质完整性,其中初级上拉预驱动器,次级上拉电路中的至少一个 预驱动器,主下拉预驱动器和辅助下拉预驱动器被配置为提供大于或等于接地电压并小于或等于电源电压的电压。

    Methods, devices, and systems for a high voltage tolerant buffer
    6.
    发明授权
    Methods, devices, and systems for a high voltage tolerant buffer 有权
    用于高电压容限缓冲器的方法,设备和系统

    公开(公告)号:US08004313B2

    公开(公告)日:2011-08-23

    申请号:US12577506

    申请日:2009-10-12

    IPC分类号: H03K19/0175

    CPC分类号: H03K19/01721

    摘要: Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a plurality of pre-drivers wherein each pre-driver of the plurality of pre-drivers is operably coupled to a transistor of a plurality of transistors. The buffer may further comprise one or more clamping devices, wherein at least one transistor of the plurality of transistors has a gate coupled to at least one clamping device of the one or more clamping devices.

    摘要翻译: 公开了方法,装置和系统,包括用于具有被配置为向薄栅介质晶体管提供电压的预驱动器电路的缓冲器。 一个这样的缓冲器可以包括多个预驱动器,其中多个预驱动器中的每个预驱动器可操作地耦合到多个晶体管的晶体管。 缓冲器还可以包括一个或多个钳位装置,其中多个晶体管中的至少一个晶体管具有耦合到一个或多个钳位装置的至少一个夹持装置的栅极。

    Write command and write data timing circuit and methods for timing the same
    7.
    发明授权
    Write command and write data timing circuit and methods for timing the same 有权
    写命令和写数据定时电路和定时方法相同

    公开(公告)号:US07969813B2

    公开(公告)日:2011-06-28

    申请号:US12416761

    申请日:2009-04-01

    IPC分类号: G11C8/00

    摘要: Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.

    摘要翻译: 用于锁存写命令的电路,存储器和方法,并且稍后提供包括写命令和写数据定时电路的写数据。 一个这样的定时电路包括内部写入命令锁存器,以响应写入命令锁存信号来锁存内部写入命令。 在延迟延迟之后,内部写命令锁存器响应于写命令锁存信号释放锁存的写命令。 定时电路还包括写平均触发器(FF)电路和写数据寄存器。 一种这样的方法包括产生和锁定内部写命令。 锁存的内部写入命令在响应于存储器时钟信号的延迟延迟之后被释放。 内部写入命令通过内部写命令路径进行传播。 写数据被捕获,并且内部写命令响应于写时钟信号而被锁存。 捕获的写入数据被释放以写入存储器。

    Multiple subscription subscriber identity module (SIM) card
    8.
    发明授权
    Multiple subscription subscriber identity module (SIM) card 有权
    多个订阅用户识别模块(SIM)卡

    公开(公告)号:US07613480B2

    公开(公告)日:2009-11-03

    申请号:US10750195

    申请日:2003-12-31

    申请人: Jason Brown

    发明人: Jason Brown

    IPC分类号: H04B1/38

    摘要: Embodiments of the invention include a multiple subscription subscriber identity module (SIM) card. The SIM card includes a plurality of sets of subscription parameters from which to select and activate a single set of parameters. The sets of subscription parameters each contain various information, e.g., information such as an Integrated Circuit Card Identifier (ICCID) and an International Mobile Subscriber Identity (IMSI), and are based on various criteria, e.g., different service regions of use for the electronic device on which the SIM card is installed. A set of subscription parameters is selected for a particular region of use either manually or automatically. The SIM card, which can include a software interface that provides a list of available sets of subscription parameters, is activated by updating the selected set of subscription parameters. Alternatively, a default set of subscription parameters is selected unless a different set of subscription parameters is selected manually from among the plurality of sets of subscription parameters. According to alternative embodiments of the invention, the selected set of subscription parameters can be deactivated and a different set of subscription parameters can be selected and updated to in the SIM card.

    摘要翻译: 本发明的实施例包括多个订阅订户身份模块(SIM)卡。 SIM卡包括多组订阅参数,从中选择和激活一组参数。 订阅参数集合各自包含各种信息,例如诸如集成电路卡标识符(ICCID)和国际移动用户标识(IMSI)的信息,并且基于各种标准,例如用于电子的不同服务区域 设备上安装了SIM卡。 手动或自动为特定使用区域选择一组订阅参数。 可以通过更新所选择的订阅参数集来激活SIM卡,该SIM卡可以包括提供可用订阅参数集合的列表的软件接口。 或者,选择默认的订阅参数集合,除非从多个订阅参数集中手动选择不同的订阅参数集合。 根据本发明的替代实施例,可以取消所选择的订阅参数集合,并且可以在SIM卡中选择并更新不同的订阅参数集合。