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公开(公告)号：US5337269A
公开(公告)日：1994-08-09
申请号：US27504
申请日：1993-03-05
CPC分类号： G06F7/506
摘要： A carry skip adder uses independent paths for propagating a skip carry bit and a carry-in bit. Propagation of the carry-in bit is inhibited during a first portion of the clock cycle to prevent spurious carry-in signals from affecting the operation. During this period, other logic functions may be performed, including calculation of the propagation bits and generate bits for each adder block.
摘要翻译： 进位跳变加法器使用独立的路径来传播跳过进位位和进位位。 在时钟周期的第一部分期间禁止进位输入位的传播，以防止寄生输入信号影响操作。 在此期间，可以执行其他逻辑功能，包括传播位的计算，并为每个加法器块生成位。
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2.发明授权Branch processing unit with a far target cache accessed by indirection from the target cache 失效具有远程目标缓存的分支处理单元通过间接从目标缓存访问
公开(公告)号：US5740416A
公开(公告)日：1998-04-14
申请号：US606668
申请日：1996-02-26
申请人： Steven C. McMahan
发明人： Steven C. McMahan
CPC分类号： G06F9/3844 , G06F12/0864 , G06F9/3806 , G06F9/3812 , G06F9/3863
摘要： A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. In one embodiment, the BPU includes a target cache and a separate far target cache--the far target cache stores limits and mode bits for far targets stored in the target cache. For each far COF entry in the target cache, an FTC index field stores an index pointing to the corresponding entry in the far target cache. For far COFs that hit in the target cache, the target cache outputs corresponding far target addressing information and the associated FTC index to indirectly access the far target cache to obtain the associated segment limit information.
摘要翻译： 在示例性实施例中，在与x86指令集架构兼容的超标量超级流水线微处理器中使用分支处理单元（BPU）。 在一个实施例中，BPU包括目标高速缓存和单独的远目标高速缓存 - 远目标缓存存储存储在目标高速缓存中的远目标的限制和模式位。 对于目标缓存中的每个远的COF条目，FTC索引字段存储指向远目标高速缓存中的对应条目的索引。 对于在目标缓存中击中的远的COF，目标缓存器输出相应的远目标寻址信息和相关联的FTC索引以间接访问远目标缓存以获得相关联的段限制信息。
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3.发明授权Branch processing unit with a return stack including repair using pointers from different pipe stages 失效分支处理单元具有返回堆栈，包括使用来自不同管段的指针进行修复
公开(公告)号：US5706491A
公开(公告)日：1998-01-06
申请号：US606667
申请日：1996-02-26
申请人： Steven C. McMahan
发明人： Steven C. McMahan
CPC分类号： G06F9/3844 , G06F12/0864 , G06F9/30054 , G06F9/3806 , G06F9/3812 , G06F9/3863
摘要： A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a return stack for call/returns, including return stack pointer repair in the case of the failure of a call/return to confirm (decode) or resolve. Return stack control logic maintains a return stack pointer, incrementing and decrementing the return stack pointer respectively for call/return pairs that hit in the target cache--in addition, the return stack control logic maintains two additional stack pointers used for repair: (a) a confirmation pointer that is incremented when a call is decoded and decremented when a return is decoded; and (b) a resolution pointer that is incremented when a call resolves, and decremented when a return resolves. If a call/return pair that hits in the target cache is not confirmed, the return stack control logic selectively repairs the return stack pointer by replacing it with the confirmation pointer, while if a call/return pair that hits in the target cache does not resolve, the return stack control logic selectively repairs the return stack pointer by replacing it with the resolution pointer.
摘要翻译： 在示例性实施例中，在与x86指令集架构兼容的超标量超级流水线微处理器中使用分支处理单元（BPU）。 BPU包括用于调用/返回的返回栈，包括在调用/返回失败以确认（解码）或解析的情况下的返回堆栈指针修复。 返回堆栈控制逻辑维护一个返回堆栈指针，分别递增和递减返回堆栈指针，用于在目标高速缓存中命中的调用/返回对 - 此外，返回堆栈控制逻辑维护两个用于修复的额外堆栈指针：（a） 一个确认指针，当一个呼叫被解码并在返回被解码时递减; 和（b）一个分辨率指针，当一个调用被解析时递增，当一个返回值解析时递减。 如果没有确认目标缓存中的命中/返回对，则返回栈控制逻辑通过用确认指针替换返回堆栈指针来选择性地修复返回栈指针，而如果在目标高速缓存中命中的调用/返回对不 解决方案，返回堆栈控制逻辑通过用分辨率指针替换来选择性地修复返回堆栈指针。
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4.发明授权
公开(公告)号：US5771365A
公开(公告)日：1998-06-23
申请号：US396857
申请日：1995-03-01
申请人： Steven C. McMahan , Mark W. Bluhm
发明人： Steven C. McMahan , Mark W. Bluhm
CPC分类号： G06F9/30167 , G06F9/261 , G06F9/265 , G06F9/28 , G06F9/30145
摘要： A microarchitecture in a complex instruction computer system is disclosed employing a sparse microROM array and concatenation address circuitry for forming microaddress entry points, avoiding the need for a programmable logic array to translate instruction opcodes and avoiding duplicative entry points, thus minimizing the microROM array size.
摘要翻译： 公开了一种复杂指令计算机系统中的微架构，其使用用于形成微地址入口点的稀疏微阵列和级联地址电路，避免了对可编程逻辑阵列转换指令操作码并避免重复入口点的需要，从而使微ROM阵列尺寸最小化。
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5.发明授权
公开(公告)号：US5644741A
公开(公告)日：1997-07-01
申请号：US138855
申请日：1993-10-18
CPC分类号： G06F9/265 , G06F9/28 , G06F9/30145
摘要： A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memory circuitry. Finally, the processor includes decode circuitry coupled to the storage circuitry for detecting whether the instruction stored in the storage circuitry comprises a single clock instruction before the memory circuit outputs the microinstruction, and for indicating to the sequencing circuitry in response to detecting whether the instruction stored in the storage circuitry comprises a single clock instruction.
摘要翻译： 处理器包括存储电路，用于存储可由微地址寻址的指令和存储器电路，用于响应于微地址输出微指令。 处理器还包括被连接以向存储器电路提供微地址的排序电路。 最后，处理器包括耦合到存储电路的解码电路，用于检测存储在存储电路中的指令是否在存储器电路输出微指令之前包括单个时钟指令，并且响应于检测指令是否存储 在存储电路中包括单个时钟指令。
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6.发明授权
公开(公告)号：US5294845A
公开(公告)日：1994-03-15
申请号：US931187
申请日：1992-08-17
申请人： Steven C. McMahan , Kenneth C. Scheuer , William B. Ledbetter, Jr. , Michael G. Gallup , James G. Gay
发明人： Steven C. McMahan , Kenneth C. Scheuer , William B. Ledbetter, Jr. , Michael G. Gallup , James G. Gay
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/003
CPC分类号： H03K19/017581 , H03K19/0005
摘要： A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.
摘要翻译： 数据处理器具有至少一个输出端，数据处理器的用户可以根据数据处理器的应用环境来改变其输出阻抗。 输出缓冲级的第一输出缓冲器具有预定的输出阻抗，并且耦合在级的输入端和输出端子之间。 第一输出缓冲器提供第一输出端阻抗。 具有比第一输出缓冲器更低的输出阻抗的第二输出缓冲器可以与第一输出缓冲器并联选择性地耦合，以减小输出端子的输出阻抗。 输出缓冲器的耦合由数据处理器的用户控制，数据处理器的用户提供用于选择多个预定输出端子阻抗值之一的控制输入。
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公开(公告)号：US07007211B1
公开(公告)日：2006-02-28
申请号：US10264551
申请日：2002-10-04
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/24 , G11C29/44 , G11C29/787 , G11C2029/1208 , G11C2029/4402
摘要： Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.
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公开(公告)号：US5835949A
公开(公告)日：1998-11-10
申请号：US831842
申请日：1997-04-02
IPC分类号： G06F9/38
CPC分类号： G06F9/3812
摘要： A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction cache from which the instructions originate.
摘要翻译： 公开了一种在流水线处理器中容易地识别和处理自修改可变长度指令的系统和方法，其采用与执行流水线的每个级相关联的索引标签，其中索引标签识别指令来自的指令高速缓存中的高速缓存行数 。
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9.发明授权Prefetch buffer using flow control bit to identify changes of flow within the code stream 失效预取缓冲区使用流控制位来识别代码流内的流程变化
公开(公告)号：US5692168A
公开(公告)日：1997-11-25
申请号：US607539
申请日：1996-02-27
申请人： Steven C. McMahan
发明人： Steven C. McMahan
CPC分类号： G06F9/3844 , G06F12/0864 , G06F9/30054 , G06F9/3806 , G06F9/3812 , G06F9/3863
摘要： A prefetch unit includes flow control for controlling the transfer of instruction bytes from a prefetch buffer to a decoder where the prefetch buffer includes predicted change of flow instructions. Instruction bytes in the prefetch buffer are arranged in prefetch blocks--associated with each prefetch block is a flow control bit. When the transfer of instruction bytes from a current prefetch block is complete, the flow control bit is checked--if the flow control bit is set to indicate that the prefetch clock includes a predicted COF instruction, instruction bytes will not be transferred from the next prefetch block unless the predicted COF instruction is confirmed as having been decoded. This flow control avoids the complexity of maintaining information to repair the prefetcher and decoder if the predicted COF instruction is not decoded.
摘要翻译： 预取单元包括流控制，用于控制指令字节从预取缓冲器到解码器的传送，其中预取缓冲器包括预测的流指令变化。 预取缓冲器中的指令字节被布置在预取块中，与每个预取块相关联是流控制位。 当来自当前预取块的指令字节的传送完成时，检查流控制位 - 如果流控制位被设置为指示预取时钟包括预测的COF指令，指令字节将不会从下一个预取 除非预测的COF指令被确认为已被解码。 如果预测的COF指令未解码，则该流控制避免维护信息以修复预取器和解码器的复杂性。
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10.发明授权Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline 失效具有多个执行管线的处理器，使用管段状态信息来控制执行管线的管段之间的指令的独立移动
公开(公告)号：US6138230A
公开(公告)日：2000-10-24
申请号：US902908
申请日：1997-07-29
CPC分类号： G06F9/3861 , G06F9/3838 , G06F9/3853 , G06F9/3867 , G06F9/3875
摘要： A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions has a data dependency on other of the simultaneously issued instructions, detecting circuitry for detecting dependencies between instructions in the pipelines and circuitry for controlling the flow of instructions through the pipelines such that an instruction is not delayed due to a data dependency on another instruction unless the data dependency must be resolved for proper processing of the instruction in its current stage.
摘要翻译： 微处理器包括具有用于处理指令流的多个级的多条指令流水线，用于同时将指令发布到两条或更多条流水线中的电路，而不考虑同时发出的指令之一是否具有与其他 同时发出的指令，用于检测管道中的指令之间的依赖性的检测电路和用于控制通过管线的指令流的电路，使得由于对另一指令的数据依赖性而不指示指令，否则指令不被延迟，除非必须解决数据依赖性以进行适当的处理 的指示在当前阶段。
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