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1.发明授权
公开(公告)号：US5162672A
公开(公告)日：1992-11-10
申请号：US632901
申请日：1990-12-24
申请人： Steven C. McMahan , Kenneth C. Scheuer , William B. Ledbetter, Jr. , Michael G. Gallup , James G. Gay
发明人： Steven C. McMahan , Kenneth C. Scheuer , William B. Ledbetter, Jr. , Michael G. Gallup , James G. Gay
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/017581 , H03K19/0005
摘要： A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance then the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.
摘要翻译： 数据处理器具有至少一个输出端，数据处理器的用户可以根据数据处理器的应用环境来改变其输出阻抗。 输出缓冲级的第一输出缓冲器具有预定的输出阻抗，并且耦合在级的输入端和输出端子之间。 第一输出缓冲器提供第一输出端阻抗。 具有较低输出阻抗的第二输出缓冲器然后与第一输出缓冲器可以被选择性地耦合到第一输出缓冲器以减小输出端子的输出阻抗。 输出缓冲器的耦合由数据处理器的用户控制，数据处理器的用户提供用于选择多个预定输出端子阻抗值之一的控制输入。
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2.发明授权
公开(公告)号：US5294845A
公开(公告)日：1994-03-15
申请号：US931187
申请日：1992-08-17
申请人： Steven C. McMahan , Kenneth C. Scheuer , William B. Ledbetter, Jr. , Michael G. Gallup , James G. Gay
发明人： Steven C. McMahan , Kenneth C. Scheuer , William B. Ledbetter, Jr. , Michael G. Gallup , James G. Gay
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/003
CPC分类号： H03K19/017581 , H03K19/0005
摘要： A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.
摘要翻译： 数据处理器具有至少一个输出端，数据处理器的用户可以根据数据处理器的应用环境来改变其输出阻抗。 输出缓冲级的第一输出缓冲器具有预定的输出阻抗，并且耦合在级的输入端和输出端子之间。 第一输出缓冲器提供第一输出端阻抗。 具有比第一输出缓冲器更低的输出阻抗的第二输出缓冲器可以与第一输出缓冲器并联选择性地耦合，以减小输出端子的输出阻抗。 输出缓冲器的耦合由数据处理器的用户控制，数据处理器的用户提供用于选择多个预定输出端子阻抗值之一的控制输入。
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3.发明授权Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation 失效数据处理器集成电路，具有可选择的复用/非复用地址和数据操作模式
公开(公告)号：US5086407A
公开(公告)日：1992-02-04
申请号：US361539
申请日：1989-06-05
申请人： Ralph C. McGarity , William B. Ledbetter, Jr. , Steven C. McMahan , Michael G. Gallup , Russell Stanphill , James G. Gay
发明人： Ralph C. McGarity , William B. Ledbetter, Jr. , Steven C. McMahan , Michael G. Gallup , Russell Stanphill , James G. Gay
CPC分类号： G06F13/4208 , G06F15/7832
摘要： A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division multiplexed with data bits when both are written to external circuitry. In a second or normal mode, the circuit's address and data terminals are not connected and address bits are communicated with the circuit independent of data bits which are communicated with the circuit. No circuitry external to the integrated circuit is required to implement the multiplexed mode. A control portion insures that bit collisions are avoided when the circuit is in the multiplexed mode.
摘要翻译： 具有可被编程为将电路的地址和数据总线端子置于两种模式之一的输入的单芯片数据处理器集成电路。 在第一或多路复用模式下，电路的地址和数据终端直接连接，并且当两者都写入外部电路时，地址位与数据位进行时分复用。 在第二或正常模式下，电路的地址和数据端子不连接，地址位与电路无关地与电路通信的数据位通信。 需要集成电路外部的电路来实现复用模式。 控制部分确保当电路处于复用模式时避免位冲突。
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4.发明授权Integrated circuit having an on chip thermal circuit requiring only one dedicated integrated circuit pin and method of operation 失效具有片上热电路的集成电路仅需要一个专用集成电路引脚和操作方法
公开(公告)号：US5477076A
公开(公告)日：1995-12-19
申请号：US297280
申请日：1994-08-29
CPC分类号： H01L27/0248 , G01K7/01 , H01L23/34 , H01L2924/0002 , H01L2924/3011
摘要： An integrated circuit implements an on chip thermal circuit (12) for measuring temperature of an operating integrated circuit die (10) by requiring only one dedicated integrated circuit pin (16). A second integrated circuit pin (18) is utilized but is also connected directly connected to other circuitry (14) on the integrated circuit and is used by the other circuitry at the same time that the integrated circuit die temperature is being measured. In one form, the second integrated circuit pin is a ground terminal. Error voltages coupled to the ground terminal may be removed from the temperature calculation by an external differential amplifier (24).
摘要翻译： 集成电路实现片上热电路（12），用于通过仅需要一个专用集成电路引脚（16）来测量工作集成电路管芯（10）的温度。 第二集成电路引脚（18）被使用，但是也被连接成直接连接到集成电路上的其它电路（14），并且被其他电路用于测量集成电路管芯温度的同时。 在一种形式中，第二集成电路引脚是接地端子。 耦合到接地端子的误差电压可以由外部差分放大器（24）从温度计算中去除。
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5.发明授权
公开(公告)号：US5467455A
公开(公告)日：1995-11-14
申请号：US145117
申请日：1993-11-03
CPC分类号： H03H7/40
摘要： A data processing system and a method for performing dynamic bus signal termination uses a dynamic bus termination circuitry (14 or 16) with a device (10 or 12). The circuitry is enabled when data is incoming to the device and is disabled when data is outgoing from the device to selectively reduce unwanted signal reflection at the signal end of a bi-directional bus (17). The disabling allows the circuitry to be removed or tristated from any connection with the bus (17) when not needed (i.e., data outgoing) to reduce loading. The disabling of the termination circuitry also aids in reducing the power consumption of the part when either the bus is sitting idle or the part is in a low power mode of operation.
摘要翻译： 用于执行动态总线信号终止的数据处理系统和方法使用具有设备（10或12）的动态总线终端电路（14或16）。 当数据进入设备时，电路被使能，并且当数据从设备输出时被禁用，以选择性地减少在双向总线（17）的信号端的不期望的信号反射。 禁用允许在不需要（即，数据输出）时，将电路从与总线（17）的任何连接中去除或三态化以减少负载。 终端电路的禁用还有助于在总线空闲或部件处于低功耗工作模式时减少部件的功耗。
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6.发明授权Integrated circuit having an on chip thermal circuit requiring only one dedicated integrated circuit pin and method of operation 失效具有片上热电路的集成电路仅需要一个专用集成电路引脚和操作方法
公开(公告)号：US5376819A
公开(公告)日：1994-12-27
申请号：US158323
申请日：1993-11-29
CPC分类号： H01L27/0248 , G01K7/01 , H01L23/34 , H01L2924/0002 , H01L2924/3011
摘要： An integrated circuit implements an on chip thermal circuit (12) for measuring temperature of an operating integrated circuit die (10) by requiring only one dedicated integrated circuit pin (16). A second integrated circuit pin (18) is utilized but is also connected directly connected to other circuitry (14) on the integrated circuit and is used by the other circuitry at the same time that the integrated circuit die temperature is being measured. In one form, the second integrated circuit pin is a ground terminal. Error voltages coupled to the ground terminal may be removed from the temperature calculation by an external differential amplifier (24).
摘要翻译： 集成电路实现片上热电路（12），用于通过仅需要一个专用集成电路引脚（16）来测量工作集成电路管芯（10）的温度。 第二集成电路引脚（18）被使用，但是也被连接成直接连接到集成电路上的其它电路（14），并且被其他电路用于测量集成电路管芯温度的同时。 在一种形式中，第二集成电路引脚是接地端子。 耦合到接地端子的误差电压可以由外部差分放大器（24）从温度计算中去除。
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7.发明授权Integrated circuit having a control signal for identifying coinciding active edges of two clock signals 失效集成电路具有用于识别两个时钟信号的重合有效边沿的控制信号
公开(公告)号：US5485602A
公开(公告)日：1996-01-16
申请号：US172985
申请日：1993-12-27
CPC分类号： G06F13/4217
摘要： A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs operations in response to the CLK signal. The bus is allowed to operate at a frequency which is less than or equal to the operational frequency of the CLK. The bus clock is typically either equal to the clock in frequency or runs at one-half or one-quarter speed. A CLKEN* signal input to the processor (10) is asserted to indicate an active edge of the external bus clock and synchronize the active edge of the external bus clock with an active edge of CLK to allow an active edge of CLK to perform bus operations which coincide with the active edge of the external bus clock. In another form, an internal counter/control circuit (20) may be used internal to the processor (10) to generate internal CLKEN* signals.
摘要翻译： 数据处理系统接收用于执行数据处理器（10）内部的操作的CLK信号。 数据处理器（10）具有响应于CLK信号执行操作的CPU（12）。 允许总线以小于或等于CLK工作频率的频率工作。 总线时钟通常等于时钟频率或以一半或四分之一速度运行。 输入到处理器（10）的CLKEN *信号被断言以指示外部总线时钟的有效边沿，并且将外部总线时钟的有效边沿与CLK的有效边沿同步，以允许CLK的有效沿执行总线操作 这与外部总线时钟的有效边沿一致。 在另一种形式中，内部计数器/控制电路（20）可以在处理器（10）内部使用，以产生内部CLKEN *信号。
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8.发明授权Synchronous bus lock mechanism permitting bus arbiter to change bus master during a plurality of successive locked operand transfer sequences after completion of current sequence 失效同步总线锁定机制允许总线仲裁器在完成当前序列之后的多个连续的锁定操作数传送序列期间改变总线主机
公开(公告)号：US5127089A
公开(公告)日：1992-06-30
申请号：US374906
申请日：1989-07-03
IPC分类号： G06F13/364 , G06F15/17
CPC分类号： G06F13/364 , G06F15/17
摘要： A data processing system having a mechanism for changing communication bus mastership when a series of locked operand transfer sequences are executed. The system has at least two processors coupled via the communication bus and a bus arbiter. In one form, a locked transfer end signal is provided by each processor to the bus arbiter so that if a high priority need is recognized by the bus arbiter during early execution of a plurality of locked operand transfer sequences the high priority need can be responded to by the bus arbiter before completion of all of the locked sequences. In another form, control signals are provided by the bus arbiter to each processor to accomplish the equivalent function.
摘要翻译： 一种数据处理系统，具有当执行一系列锁定操作数传送序列时改变通信总线主管性的机制。 该系统具有经由通信总线和总线仲裁器耦合的至少两个处理器。 在一种形式中，锁定的传送结束信号由每个处理器提供给总线仲裁器，使得如果在多个锁定的操作数传送序列的早期执行期间由总线仲裁器识别到高优先级的需要，则可以对高优先级的需求作出响应 由总线仲裁器完成所有的锁定序列。 在另一种形式中，控制信号由总线仲裁器提供给每个处理器以实现等效功能。
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公开(公告)号：US5872940A
公开(公告)日：1999-02-16
申请号：US627669
申请日：1996-04-01
CPC分类号： G06F13/1694
摘要： A system bus controller (103) within a processor (101) includes programmable logic for different modes of chip enable signals on a per-address-space basis. This allows for a "glueless" interface (107) between the processor (101) and different types of external devices (111, 112, 113), such as memory devices. A chip select register value 604, 608, 612 is preprogrammed with respect to each external device coupled to the processor (101). This preprogrammed register value 604, 608, 612 is used by the system bus controller (103) to uniquely configure a read/write access signal to be sent to each of the external devices (111, 112, 113).
摘要翻译： 处理器（101）内的系统总线控制器（103）包括用于每个地址空间的不同模式的芯片使能信号的可编程逻辑。 这允许在处理器（101）和不同类型的外部设备（111,112,113）之间的诸如存储器设备之间的“无胶粘”接口（107）。 相对于耦合到处理器（101）的每个外部设备，对芯片选择寄存器值604,608,612进行预编程。 系统总线控制器（103）使用该预编程寄存器值604,608,612来唯一地配置要发送到每个外部设备（111,112,113）的读/写访问信号。
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10.发明授权Method and apparatus for accessing a chip-selectable device in a data processing system 失效用于在数据处理系统中访问芯片可选设备的方法和装置
公开(公告)号：US5740382A
公开(公告)日：1998-04-14
申请号：US623482
申请日：1996-03-28
CPC分类号： G06F13/1694
摘要： A user may program a data processor (3) such that external master chip select accesses can be either the same or different length of time than an internal master access through the use of a control register (810). Additionally, the user can turn off the internal transfer acknowledge logic and add external transfer acknowledge logic while still using the internal chip select and write enable generation logic (8) of the data processor. This feature is user programmable on a chip select basis and provides a flexible solution which allows the user to compensate for different external master accesses without requiring external chip select and write enable logic. Therefore, overhead is conserved and efficiency is increased.
摘要翻译： 用户可以对数据处理器（3）进行编程，使得通过使用控制寄存器（810），外部主芯片选择访问可以与内部主机访问相同或不同的时间长度。 此外，用户可以在仍然使用数据处理器的内部芯片选择和写入使能生成逻辑（8）的同时关闭内部传输确认逻辑并添加外部传输确认逻辑。 该功能是用户可编程的芯片选择基础，并提供灵活的解决方案，允许用户补偿不同的外部主访问，而不需要外部芯片选择和写使能逻辑。 因此，节省开销，提高效率。
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