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公开(公告)号：US6014755A
公开(公告)日：2000-01-11
申请号：US700676
申请日：1996-08-12
CPC分类号： G11C29/765 , G06F11/1068 , G11C29/4401 , G11C29/88 , G11C2029/0409
摘要： A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.
摘要翻译： 一种用于监视闪存阵列的操作的方法，所述闪速存储器阵列被划分成单独的可擦除存储块，以便确保存储在阵列中的数据的完整性，其中每个读取或写入操作被验证以检测可能在操作中发生的错误 包括以下步骤：每当发生错误以进行错误发生以尝试至少一次重试操作以确定该错误是否可重复时，如果该错误被发现是可重复的，则应该从该块中删除指示有效数据的块，从该块中删除有效信息 如果发现错误是可重复的，并且从操作中移除具有可重复错误的块，则阻塞。
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公开(公告)号：US5577194A
公开(公告)日：1996-11-19
申请号：US511990
申请日：1995-08-07
CPC分类号： G11C29/765 , G06F11/1068 , G11C29/4401 , G11C29/88 , G11C2029/0409
摘要： A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.
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公开(公告)号：US5473753A
公开(公告)日：1995-12-05
申请号：US969749
申请日：1992-10-30
CPC分类号： G11C29/765 , G06F11/1068 , G11C29/4401 , G11C29/88 , G11C2029/0409
摘要： A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.
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4.发明授权Method for assuring that an erase process for a memory array has been properly completed 失效确保存储器阵列的擦除处理已经被正确完成的方法
公开(公告)号：US5369616A
公开(公告)日：1994-11-29
申请号：US207228
申请日：1994-03-07
申请人： Steven E. Wells , Eric J. Magnusson
发明人： Steven E. Wells , Eric J. Magnusson
CPC分类号： G06F3/0601 , G11C16/102 , G11C16/16 , G06F2003/0694
摘要： A method for insuring that an erase operation practiced on a block of flash EEPROM transistors is carried out reliably including the steps of: writing whenever the erasure of a block of the flash EEPROM array is to commence to a position in the array to indicate that an erasure of the block has commenced, writing whenever the erasure of a block of the flash EEPROM array is complete to the position in the array to indicate that an erasure of the block has been completed, testing to determine any positions in the array which indicate that an erasure of a block has commenced but not been completed upon applying power to the flash EEPROM array, and reinitiating an erase if any positions in the array exist which indicate that an erasure of a block has commenced but not been completed.
摘要翻译： 一种用于确保在快闪EEPROM晶体管块上实施的擦除操作被可靠地执行的方法，包括以下步骤：每当闪存EEPROM阵列的块的擦除开始到阵列中的位置时写入，以指示 块的擦除已经开始，每当擦除快闪EEPROM阵列的块完成到阵列中的位置以指示块的擦除已经完成时，写入测试来确定阵列中的任何位置，表示该块 块的擦除已经开始，但是在向闪存EEPROM阵列施加电力时未完成，并且如果存在阵列中的任何位置，则重新启动擦除，这表示块的擦除已经开始但未完成。
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5.发明授权Method for assuring that an erase process for a memory array has been properly completed 失效确保存储器阵列的擦除处理已经被正确完成的方法
公开(公告)号：US5544119A
公开(公告)日：1996-08-06
申请号：US522980
申请日：1995-09-06
申请人： Steven E. Wells , Eric J. Magnusson
发明人： Steven E. Wells , Eric J. Magnusson
CPC分类号： G06F3/0601 , G11C16/102 , G11C16/16 , G06F2003/0694
摘要： A method for insuring that an erase operation practiced on a block of flash EEPROM transistors is carried out reliably including the steps of: writing whenever the erasure of a block of the flash EEPROM array is to commence to a position in the array to indicate that an erasure of the block has commenced, writing whenever the erasure of a block of the flash EEPROM array is complete to the position in the array to indicate that an erasure of the block has been completed, testing to determine any positions in the array which indicate that an erasure of a block has commenced but not been completed upon applying power to the flash EEPROM array, and reinitiating an erase if any positions in the array exist which indicate that an erasure of a block has commenced but not been completed.
摘要翻译： 一种用于确保在快闪EEPROM晶体管块上实施的擦除操作被可靠地执行的方法，包括以下步骤：每当闪存EEPROM阵列的块的擦除开始到阵列中的位置时写入，以指示 块的擦除已经开始，每当擦除快闪EEPROM阵列的块完成到阵列中的位置以指示块的擦除已经完成时，写入测试来确定阵列中的任何位置，表示该块 块的擦除已经开始，但是在向闪存EEPROM阵列施加电力时未完成，并且如果存在阵列中的任何位置，则重新启动擦除，这表示块的擦除已经开始但未完成。
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公开(公告)号：US07177888B2
公开(公告)日：2007-02-13
申请号：US10633096
申请日：2003-08-01
申请人： Steven E. Wells
发明人： Steven E. Wells
CPC分类号： H03K3/84 , H03K3/017 , H03K5/1565
摘要： A method of producing a uniform duty cycle output from a random bit source. The method includes testing the duty cycle of said random bit source; varying the output voltage of a voltage source if the duty cycle is not substantially fifty percent; and iteratively altering the output voltage of the voltage source until said duty cycle is substantially fifty percent.
摘要翻译： 从随机位源产生均匀占空比的方法。 该方法包括测试所述随机位源的占空比; 如果占空比基本上不是百分之五十，则改变电压源的输出电压; 并且迭代地改变电压源的输出电压，直到所述占空比大致为百分之五十。
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公开(公告)号：US07085341B2
公开(公告)日：2006-08-01
申请号：US10614966
申请日：2003-07-08
申请人： Steven E. Wells
发明人： Steven E. Wells
IPC分类号： G06M3/00
CPC分类号： H03K21/403
摘要： A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.
摘要翻译： 非易失性计数器。 非易失性存储器以不均匀基数的数字组织。 提供电路以增加响应于增量命令由数字表示的计数值。
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公开(公告)号：US5835933A
公开(公告)日：1998-11-10
申请号：US19766
申请日：1993-02-19
CPC分类号： G06F3/0607 , G06F3/0632 , G06F3/0676 , G06F8/65
摘要： A method for updating the content of EEPROM memory used for controlling processes run on a microprocessor used to control the operations of a long term memory array which includes moving an update process stored in the EEPROM memory to a random access memory associated with the microprocessor; and then using the update process stored in random access memory for erasing the contents of the EEPROM memory, and furnishing data to the microprocessor on a sector by sector basis from a host computer through an interface used by the microprocessor to provide data to the long term memory array. The data furnished by the host is written sector by sector to the EEPROM memory until the EEPROM memory has been updated.
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9.发明授权Method and apparatus for retaining flash block structure data during erase operations in a flash EEPROM memory array 失效用于在闪存EEPROM存储器阵列中的擦除操作期间保持闪存块结构数据的方法和装置
公开(公告)号：US5581723A
公开(公告)日：1996-12-03
申请号：US20204
申请日：1993-02-19
申请人： Robert N. Hasbun , Steven E. Wells
发明人： Robert N. Hasbun , Steven E. Wells
CPC分类号： G06F3/0601 , G06F12/0246 , G06F11/1435 , G06F2003/0694
摘要： A method for reliably storing management data in a flash EEPROM memory array, which array is divided into a plurality of individually-erasable blocks of memory cells and in which each of the blocks of memory cells has stored thereon data regarding management of the array during a cleanup process in which valid data stored in a first block is written to another block of the array, and then the first block is erased. The process includes the steps of storing data regarding management of the array from the first block in random access memory and, in an enhanced process, on another block before erasure of the first block. The data may then be rewritten to the first block after the erase. With the enhanced process, a special identification is provided to the data regarding the management of the array stored on another block which is outside the normal identification range for the host computer so that the specially identified data is not lost during a power loss during an erase process and may be detected after power is restored to the system.
摘要翻译： 一种用于将快速EEPROM存储器阵列中的管理数据可靠地存储的方法，该阵列被划分为多个可单独擦除的存储器单元块，其中存储单元块中的每个块已经存储有关于在一个 清除过程，其中存储在第一块中的有效数据被写入阵列的另一个块，然后第一块被擦除。 该处理包括以下步骤：在第一块的擦除之前，将来自第一块的阵列的管理的数据存储在随机存取存储器中，并且在增强的处理中存储在另一个块上。 然后可以在擦除之后将数据重写到第一块。 通过增强处理，对存储在另一个块上的阵列的管理数据提供了特殊的标识，该数组在主计算机的正常识别范围之外，使得在擦除期间的功率损耗期间特殊识别的数据不会丢失 并且可以在电力恢复到系统之后被检测到。
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10.发明授权Addressing modes for a dynamic single bit per cell to multiple bit per cell memory 失效每个单元的动态单个位的寻址模式，每个单元存储器的多个位
公开(公告)号：US5574879A
公开(公告)日：1996-11-12
申请号：US541522
申请日：1995-10-10
申请人： Steven E. Wells , Kurt B. Robinson
发明人： Steven E. Wells , Kurt B. Robinson
CPC分类号： G11C11/5621 , G11C11/56 , G11C2211/5641 , G11C8/00
摘要： A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address buffer for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" memory cells. In order to address a portion of the "n" bits identified by a single physical address, the address buffer generates a multi-level cell (MLC) address. The memory system also contains a switch control for permitting selection a multi-level cell (MLC) mode and a standard cell mode. A select circuit permits reading a single bit per cell when the memory operates in the standard cell mode, and permits reading multiple bits of data per memory cell when the memory operates in the multi-level cell mode. The addressing scheme of the present invention maintains address coherency by exhibiting a n:1 correspondence between memory locations and the physical addresses when operating in the MLC mode, and by exhibiting a 1:1 correspondence between memory space and the physical addresses when operating in the standard cell mode.
摘要翻译： 存储器系统包含用于存储多个阈值电平的存储器单元，以表示“n”位数据的存储。 存储器系统包括用于生成多个物理地址的地址缓冲器，使得每个物理地址唯一地标识“j”个存储器单元的存储器位置。 为了寻址由单个物理地址标识的“n”位的一部分，地址缓冲器生成多级单元（MLC）地址。 存储器系统还包含用于允许选择多级单元（MLC）模式和标准单元模式的开关控制。 当存储器以标准单元模式运行时，选择电路允许每单元读取单个位，并且当存储器以多电平单元模式运行时，允许每个存储单元读取多个位数据。 本发明的寻址方案通过在以MLC模式操作时通过表现出存储器位置与物理地址之间的1对应关系来维持地址一致性，并且当在标准中操作时通过显示存储器空间和物理地址之间的1：1对应关系 单元格模式。
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