公开(公告)号：US08601233B2

公开(公告)日：2013-12-03

申请号：US13658752

申请日：2012-10-23

申请人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron B. Rust ,  Sebastian Schoenberg

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron B. Rust ,  Sebastian Schoenberg

IPC分类号： G11C15/00

CPC分类号： G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US07370160B2

公开(公告)日：2008-05-06

申请号：US11171993

申请日：2005-06-29

申请人： Gilbert Neiger ,  Steven M. Bennett ,  Andrew V. Anderson ,  Dion Rodgers ,  David Koufaty ,  Richard A. Uhlig ,  Camron B. Rust ,  Larry O. Smith ,  Rupin H. Vakharwala

发明人： Gilbert Neiger ,  Steven M. Bennett ,  Andrew V. Anderson ,  Dion Rodgers ,  David Koufaty ,  Richard A. Uhlig ,  Camron B. Rust ,  Larry O. Smith ,  Rupin H. Vakharwala

IPC分类号： G06F12/00

CPC分类号： G06F12/1009 ,  G06F9/45537

摘要： A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory location by a guest in a virtual machine executable on the processor based at least in part on a memory type field stored in an entry of an extended paging table of a virtualization support system of the host machine (extended memory type field), to determine a guest memory type for the reference to the memory location, and to determine an effective memory type based on at least one of the host memory type and the guest memory type.

摘要翻译： 能够在主机中操作的处理器，包括用于支持由处理器进行物理存储器访问的多种存储器类型的存储器管理逻辑，以及虚拟化支持逻辑，以通过以下方式来确定用于引用存储器位置的主机存储器类型 至少部分地基于存储在主机的虚拟化支持系统（扩展存储器类型字段）的扩展寻呼表的条目中的存储器类型字段来在处理器上执行的虚拟机中的客户端，以确定客户机存储器类型 用于引用存储器位置，并且基于主机存储器类型和来宾存储器类型中的至少一个来确定有效的存储器类型。

公开(公告)号：US08683158B2

公开(公告)日：2014-03-25

申请号：US11322756

申请日：2005-12-30

申请人： Martin G. Dixon ,  David A. Koufaty ,  Camron B. Rust ,  Hermann W. Gartler ,  Frank Binns

发明人： Martin G. Dixon ,  David A. Koufaty ,  Camron B. Rust ,  Hermann W. Gartler ,  Frank Binns

IPC分类号： G06F12/14

CPC分类号： G06F12/1425 ,  G06F12/1491

摘要： Apparatuses and methods for steering SMM code region accesses are disclosed. In one embodiment, an apparatus includes a status indicator, a base storage location, and an abort storage location. The status indicator is to indicate whether the apparatus is operating in SMM. The base storage location is to store a base address and the abort storage location is to store an abort address. The base address is to specify a first memory address region at which SMM code is to be accessed. The abort address is to specify a second memory address region to which accesses to the first memory address region are to be steered if the apparatus is not operating in SMM.

摘要翻译： 公开了用于转向SMM码区域访问的装置和方法。 在一个实施例中，装置包括状态指示符，基本存储位置和中止存储位置。 状态指示灯是指示设备是否在SMM中运行。 基本存储位置是存储基地址，并且中止存储位置是存储中止地址。 基地址是指定要访问SMM代码的第一个存储器地址区域。 中止地址是指定第二存储器地址区域，如果设备不在SMM中操作，则对第一存储器地址区域进行访问将被转向。

公开(公告)号：US20140189192A1

公开(公告)日：2014-07-03

申请号：US13730411

申请日：2012-12-28

申请人： Shlomo Raikin ,  Oren Hamama ,  Robert S. Chappell ,  Camron B. Rust ,  Han S. Luu ,  Leslie A. Ong ,  Gur Hildesheim

发明人： Shlomo Raikin ,  Oren Hamama ,  Robert S. Chappell ,  Camron B. Rust ,  Han S. Luu ,  Leslie A. Ong ,  Gur Hildesheim

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/652 ,  Y02D10/13

摘要： An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.

摘要翻译： 一种用于实现多页尺寸翻译后备缓冲器（TLB）的装置和方法。 例如，根据一个实施例的方法包括：从线性地址读取第一组位和第二组位; 确定线性地址是否与大页面尺寸或小页面尺寸相关联; 如果所述线性地址与第一页面尺寸相关联，则使用所述第一组位标识第一高速缓存集合，并且如果所述线性地址与第二页面尺寸相关联则使用所述第二组位标识第二高速缓存集合; 以及如果所述线性地址与第一页面尺寸相关联并且如果所述线性地址与第二页面尺寸相关联则识别第二高速缓存路线，则识别第一高速缓存路线。