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    APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB)
    1.
    发明申请
    APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB) 审中-公开
    多页翻页预处理缓存器（TLB）的设备和方法

    公开(公告)号：US20140189192A1

    公开(公告)日：2014-07-03

    申请号：US13730411

    申请日：2012-12-28

    申请人： Shlomo Raikin ,  Oren Hamama ,  Robert S. Chappell ,  Camron B. Rust ,  Han S. Luu ,  Leslie A. Ong ,  Gur Hildesheim

    发明人： Shlomo Raikin ,  Oren Hamama ,  Robert S. Chappell ,  Camron B. Rust ,  Han S. Luu ,  Leslie A. Ong ,  Gur Hildesheim

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F2212/652 ,  Y02D10/13

    摘要： An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.

    摘要翻译： 一种用于实现多页尺寸翻译后备缓冲器（TLB）的装置和方法。 例如，根据一个实施例的方法包括：从线性地址读取第一组位和第二组位; 确定线性地址是否与大页面尺寸或小页面尺寸相关联; 如果所述线性地址与第一页面尺寸相关联，则使用所述第一组位标识第一高速缓存集合，并且如果所述线性地址与第二页面尺寸相关联则使用所述第二组位标识第二高速缓存集合; 以及如果所述线性地址与第一页面尺寸相关联并且如果所述线性地址与第二页面尺寸相关联则识别第二高速缓存路线，则识别第一高速缓存路线。

    Balanced P-LRU tree for a “multiple of 3” number of ways cache
    3.
    发明授权
    Balanced P-LRU tree for a “multiple of 3” number of ways cache 有权
    平衡的P-LRU树为“多个3”的缓存方式

    公开(公告)号：US09348766B2

    公开(公告)日：2016-05-24

    申请号：US13994690

    申请日：2011-12-21

    申请人： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    发明人： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    IPC分类号： G06F13/00 ,  G06F12/12 ,  G06F3/06 ,  G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/122 ,  G06F3/0604 ,  G06F12/00 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/124 ,  G06F12/125

    摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.

    摘要翻译： 根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中，多个方式包括量是三的倍数而不是二的幂，并且其中多个方式被组织成多对。 在这种实施例中，装置还包括用于多个对中的每一对的单个比特，其中每个单个比特将用作表示相关联的一对路由的中间级别决策节点，以及具有正好两个单独比特的根级别决策节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。 还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

    Concurrent page table walker control for TLB miss handling
    6.
    发明授权
    Concurrent page table walker control for TLB miss handling 有权
    用于TLB未命中处理的并发页表步行控制

    公开(公告)号：US09069690B2

    公开(公告)日：2015-06-30

    申请号：US13613777

    申请日：2012-09-13

    申请人： Gur Hildesheim ,  Chang Kian Tan ,  Robert S. Chappell ,  Rohit Bhatia

    发明人： Gur Hildesheim ,  Chang Kian Tan ,  Robert S. Chappell ,  Rohit Bhatia

    IPC分类号： G06F12/10

    CPC分类号： G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/651 ,  G06F2212/655 ,  G06F2212/681 ,  G06F2212/684

    摘要： In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并且从寻呼结构获得物理地址的对应部分，与第一步行者并行操作的第二步行者，以及 用于防止第一步行器响应于匹配由第二步行者访问的并行寻呼结构的对应线性地址部分的第一线性地址部分而将所获得的物理地址部分存储在寻呼高速缓存器中的逻辑。 描述和要求保护其他实施例。