公开(公告)号：US08812768B2

公开(公告)日：2014-08-19

申请号：US12033577

申请日：2008-02-19

申请人： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G06F12/00

CPC分类号： G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/4243 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/1042 ,  G11C7/20 ,  G11C8/06 ,  G11C8/10 ,  Y02D10/14 ,  Y02D10/151

摘要： A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

摘要翻译： 一种在环形拓扑组织中具有串联连接的存储器件以实现高速性能的系统。 存储器件具有动态可配置的数据宽度，使得系统可以以高达最大公共数量的有源数据焊盘操作以最大化性能，或者使用单个有源数据焊盘操作以最小化功耗。 因此，系统可以包括具有不同数据宽度的存储器件的混合。 通过在广播操作中通过从存储器控制器的所有存储器装置串行传播的单个命令的发布来动态地配置存储器件。 通过实施数据输出禁止算法来确保系统的稳健运行，当从其正确的序列中接收到读取输出控制信号时，该算法防止有效数据被提供给存储器控制器。

公开(公告)号：US08407395B2

公开(公告)日：2013-03-26

申请号：US11843440

申请日：2007-08-22

申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon ,  Steven Przybylski

发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon ,  Steven Przybylski

IPC分类号： G06F12/00

CPC分类号： G11C7/1042 ,  G06F12/0623 ,  G06F13/1694 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/10 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

摘要翻译： 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

公开(公告)号：US08984249B2

公开(公告)日：2015-03-17

申请号：US11613563

申请日：2006-12-20

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Steven Przybylski

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Steven Przybylski

IPC分类号： G06F12/00 ,  G11C7/20 ,  G06F13/42 ,  G11C7/10 ,  G11C19/00 ,  G11C29/44

CPC分类号： G11C7/20 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1003 ,  G11C19/00 ,  G11C2029/4402

摘要： A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.

摘要翻译： 多个存储器件（例如，DRAM，SRAM，NAND闪存，NOR闪存）被串联连接。 每个互连设备接收设备标识符（ID）并将其锁定为其ID。 每个设备包括用于计算另一个ID或增加的ID以生成它的电路。 生成的ID被传送到另一个设备，并且ID在串行互连中的每个设备中增加。 互连中的最后一个设备提供最后生成的ID，其提供给具有从所提供的最后生成的ID识别串行互连设备的总数的识别电路的存储器控​​制器。 识别电路识别串行互连中设备的总输出延迟。

公开(公告)号：US08429495B2

公开(公告)日：2013-04-23

申请号：US12907210

申请日：2010-10-19

申请人： Steven Przybylski

发明人： Steven Przybylski

IPC分类号： G11C29/00

CPC分类号： G11C29/00 ,  G06F11/1072 ,  H03M13/036 ,  H03M13/353 ,  H03M13/49

摘要： A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.

摘要翻译： 通道具有第一和第二端。 信道的第一端耦合到发射机。 信道能够发送从从第一端到第二端的符号集中选择的符号。 该通道显示不完整的错误引入属性。 代码包括一组代码字。 代码字集合的元素是一个或多个代码符号。 代码符号是符号集的成员。 根据信道的误差引入属性，码集集合的元素之间的最小修改汉明距离大于码集集合元素之间的最小汉明距离。 还描述了存储器件，使用该通道的方法以及生成代码的方法。