公开(公告)号：US20250167736A1

公开(公告)日：2025-05-22

申请号：US18949385

申请日：2024-11-15

Applicant: Stichting IMEC Nederland

Inventor： Anoop Bhat ,  Paul Mateman

IPC: H03F1/22 ,  H03F1/26 ,  H03F1/56

Abstract: A low-noise amplifier, LNA, circuitry for amplifying an input signal to an output signal; the circuitry comprising a first cascode amplifier and a second complementary cascode amplifier, respectively connected to a first load and a second load; wherein the first load and the second load are coupled and wherein the output signal is an output of the first or second cascode amplifier; wherein the first cascode amplifier comprises a first initial amplification stage and a first transistor; wherein the second cascode amplifier comprises a second initial amplification stage, and a second transistor, arranged in a common-gate configuration, in cascode with the second initial amplification stage and connected to the second load; and wherein inputs of the first and second transistors are capacitively coupled such that the first and second transistors are connected at frequencies higher than a frequency characterising the capacitive coupling.

公开(公告)号：US20200136628A1

公开(公告)日：2020-04-30

申请号：US16670394

申请日：2019-10-31

Applicant: Stichting IMEC Nederland

Inventor： Johan van den Heuvel ,  Paul Mateman

IPC: H03L7/099 ,  H03M1/82 ,  H03L1/00

Abstract: A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

公开(公告)号：US20200044606A1

公开(公告)日：2020-02-06

申请号：US16527799

申请日：2019-07-31

Applicant: Stichting IMEC Nederland

Inventor： Paul Mateman ,  Cui Zhou

IPC: H03B5/12

Abstract: A differential Colpitts oscillator circuit is described which has center-tapped inductors which are cross-coupled with gates of second transistors of first and second transistor pairs which can reduce the minimum power supply voltage and the bias voltage for the circuit. In addition, a capacitive ladder can be implemented which also has the potential benefit of increased tuning range.

公开(公告)号：US20180337683A1

公开(公告)日：2018-11-22

申请号：US15985563

申请日：2018-05-21

Applicant: Stichting IMEC Nederland

Inventor： Paul Mateman

IPC: H03L7/099 ,  H03L7/091 ,  H04L7/033

CPC classification number: H03L7/0992 ,  H03L7/081 ,  H03L7/091 ,  H03L7/18 ,  H04L1/205 ,  H04L7/0331

Abstract: Systems and methods for providing improved linearity and reduced noise in a digital phase-locked loop in which a differential time-to-digital converter is implemented. Digital-to-time converters are used for adjusting a reference clock signal based on a fractional change signal and for adjusting a feedback signal based on another fractional change signal. Each fractional change signal is centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the fractional change signals can be described as (M+x) and (M−x), respectively. By implementing a differential time-to-digital converter, the sum of delays in each input path is kept constant so that integral non-linearity is improved. Supply sensitivity is also reduced, as the same supply is applied to both differential input paths. Since the differential delay can be both positive and negative, the delay range of a differential digital-to-time converter is half that of a single input digital-to-time converter.

公开(公告)号：US11860265B2

公开(公告)日：2024-01-02

申请号：US17386843

申请日：2021-07-28

Applicant: Stichting IMEC Nederland

Inventor： Rainer Oliver Hornung ,  Peng Zhang ,  Marco Mercuri ,  Paul Mateman ,  Lichen Yao

IPC: G01S13/42 ,  G01S7/35 ,  G01S13/58

CPC classification number: G01S13/426 ,  G01S7/354 ,  G01S7/356 ,  G01S13/584

Abstract: A method for extracting spatial resolution and/or velocity resolution of a single-input single-output radar acquiring raw radar data with a frequency scanning antenna is provided. The method includes steering a radar beam with the aid of the frequency scanning antenna with respect to an area to be illuminated by the radar, and dividing the area into at least two angular sectors. In this context, the at least two angular sectors are configured in a manner that the at least two angular sectors overlap with respect to each other.

公开(公告)号：US20220140831A1

公开(公告)日：2022-05-05

申请号：US17401924

申请日：2021-08-13

Applicant: Stichting IMEC Nederland

Inventor： Johan van den Heuvel ,  Paul Mateman ,  Yuming He

IPC: H03L7/081 ,  H03L7/099

Abstract: A circuit for facilitating random edge injection locking of an oscillator comprises a clock signal and a digitally controlled delay line, where the digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence. Moreover, the circuit comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal.

公开(公告)号：US11088664B2

公开(公告)日：2021-08-10

申请号：US16714128

申请日：2019-12-13

Applicant: Stichting IMEC Nederland

Inventor： Wilfried Zomagboguelou ,  Paul Mateman ,  Yao-Hong Liu

IPC: H03F3/72 ,  H03F3/24 ,  G06F7/58

Abstract: A signal generator is configured to generate a signal with an amplitude sweep, the signal generator having circuitry comprising: a set of control components, each control component of the set being arranged to be switchably activated in parallel in the circuitry such that an amplitude of the signal has an intrinsic dependence on the number of the control components activated; a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling activation of a respective control component of the set of control components such that the control components are arranged to be activated or de-activated in a pre-determined order by shifting activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

公开(公告)号：US10938393B2

公开(公告)日：2021-03-02

申请号：US16709604

申请日：2019-12-10

Applicant: Stichting IMEC Nederland

Inventor： Wilfried Zomagboguelou ,  Paul Mateman ,  Yao-Hong Liu

IPC: H03L7/04 ,  H03B5/12 ,  H03B5/24 ,  H03B23/00 ,  G01S13/34 ,  H03C3/00

Abstract: An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

公开(公告)号：US10819278B2

公开(公告)日：2020-10-27

申请号：US16527799

申请日：2019-07-31

Applicant: Stichting IMEC Nederland

Inventor： Paul Mateman ,  Cui Zhou

IPC: H03B5/12 ,  H03B5/18 ,  H03K3/354

Abstract: A differential Colpitts oscillator circuit is described which has center-tapped inductors which are cross-coupled with gates of second transistors of first and second transistor pairs which can reduce the minimum power supply voltage and the bias voltage for the circuit. In addition, a capacitive ladder can be implemented which also has the potential benefit of increased tuning range.

公开(公告)号：US20200044603A1

公开(公告)日：2020-02-06

申请号：US16527471

申请日：2019-07-31

Applicant: Stichting IMEC Nederland

Inventor： Cui Zhou ,  Paul Mateman

IPC: H03B5/12

Abstract: A differential Colpitts oscillator circuit is described which provides a larger tuning range, has better phase noise and uses less power than conventional differential Colpitts oscillator circuits. The circuit is characterized by a capacitive ladder in which only variable capacitor is used for tuning the circuit. In some embodiments, a variable capacitor can be used for fine tuning.