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    Quad flat non-leaded package
    1.
    发明授权
    Quad flat non-leaded package 有权
    四方扁平无铅包装

    公开(公告)号：US07141867B2

    公开(公告)日：2006-11-28

    申请号：US11170309

    申请日：2005-06-29

    申请人： Su Tao ,  Chi-Wen Chang

    发明人： Su Tao ,  Chi-Wen Chang

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49503 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

    摘要： The present invention relates to a quad flat non-leaded package comprising: a lead frame, a semiconductor chip, a plurality of connecting wires and a molding compound. The lead frame has a plurality of leads, a die pad, a plurality of supporting bars and an external ring. The external ring is disposed around the die pad and is in contact with the semiconductor chip so as to increase the supporting to the semiconductor chip. The area of the semiconductor chip is larger than that of the die pad, and the semiconductor chip is attached to the die pad through its active surface. The molding compound encapsulates the lead frame, semiconductor chip and connecting wires, wherein part of the leads of the lead frame is exposed to the outside of the molding compound so as to be electrically connected to an external device.

    摘要翻译： 本发明涉及四边形非铅包装，其包括：引线框架，半导体芯片，多个连接线和模塑料。 引线框架具有多个引线，芯片焊盘，多个支撑条和外部环。 外环设置在芯片焊盘周围并与半导体芯片接触，以增加对半导体芯片的支撑。 半导体芯片的面积大于管芯焊盘的面积，并且半导体芯片通过其有源表面附接到管芯焊盘。 模塑料封装引线框架，半导体芯片和连接线，其中引线框架的引线的一部分暴露于模制化合物的外部，以便电连接到外部装置。

    Imaging systems with fixed output sizes and frame rates
    3.
    发明授权
    Imaging systems with fixed output sizes and frame rates 有权
    具有固定输出尺寸和帧速率的成像系统

    公开(公告)号：US08526752B2

    公开(公告)日：2013-09-03

    申请号：US12861760

    申请日：2010-08-23

    申请人： Sheng Lin ,  Adam Zerwick ,  Kai Yau Mok ,  Chi-Wen Chang

    发明人： Sheng Lin ,  Adam Zerwick ,  Kai Yau Mok ,  Chi-Wen Chang

    IPC分类号： G06K9/36 ,  H04N5/228

    CPC分类号： H04N19/188 ,  H04N19/146 ,  H04N19/625 ,  H04N19/68

    摘要： An imaging system may include an image sensor and an image encoder that encodes images from the image sensor with fixed output sizes and frame rates. The image encoder may encode images from the image sensor into an image format such as a Joint Photographic Experts Group (JPEG) format. The image encoder may insert padding data between image blocks in the encoded data to compensate in real time for variations in the encoded size of an image. The amount of padding data inserted by the encoder may be calculated to ensure the encoded image has a file size close to, but not greater than, the required fixed output size. If needed, the encoder may add additional padding data after the image blocks are encoded in a blanking period before a subsequent image is encoded so that the final size of the encoded image is equal to the required output size.

    摘要翻译： 成像系统可以包括图像传感器和图像编码器，其以固定的输出尺寸和帧速率对来自图像传感器的图像进行编码。 图像编码器可以将来自图像传感器的图像编码成诸如联合图像专家组（JPEG）格式的图像格式。 图像编码器可以在编码数据中的图像块之间插入填充数据，以实时补偿图像的编码大小的变化。 可以计算由编码器插入的填充数据的量，以确保编码图像的文件大小接近但不大于所需的固定输出大小。 如果需要，编码器可以在对后续图像进行编码之前在消隐期间对图像块进行编码之后添加附加填充数据，使得编码图像的最终尺寸等于所需的输出尺寸。

    QUAD FLAT NON-LEADED PACKAGE
    4.
    发明申请
    QUAD FLAT NON-LEADED PACKAGE 有权
    QUAD平面非引线包装

    公开(公告)号：US20100219518A1

    公开(公告)日：2010-09-02

    申请号：US12578749

    申请日：2009-10-14

    申请人： Yueh-Liang Hsu ,  Chi-Wen Chang

    发明人： Yueh-Liang Hsu ,  Chi-Wen Chang

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A quad flat non-leaded package including a leadframe, a chip, a plurality of first bonding wires and a molding compound is provided. The leadframe includes a plurality of first leads, and each first lead has a first portion and a second portion that extend along an axis. The length of the first portion is greater than the length of the second portion. The thickness of the first portion is greater than the thickness of the second portion. The chip is disposed on the leadframe and covers a portion of the first portions. The first bonding wires are connected between the chip and another portion of the first portions or the chip and the second portions, such that the chip is electrically connected to the first leads through the first bonding wires. The molding compound encapsulates a portion of the first leads, the chip and the first bonding wires.

    摘要翻译： 提供了包括引线框架，芯片，多个第一接合线和模制化合物的四边形扁平非引线封装。 引线框架包括多个第一引线，并且每个第一引线具有沿轴线延伸的第一部分和第二部分。 第一部分的长度大于第二部分的长度。 第一部分的厚度大于第二部分的厚度。 芯片设置在引线框架上并覆盖第一部分的一部分。 第一接合线连接在芯片与第一部分的另一部分或芯片和第二部分之间，使得芯片通过第一接合线电连接到第一引线。 模制化合物封装了第一引线，芯片和第一接合线的一部分。

    Quad flat non-leaded package
    5.
    发明授权
    Quad flat non-leaded package 有权
    四方扁平无铅包装

    公开(公告)号：US08957506B2

    公开(公告)日：2015-02-17

    申请号：US12578749

    申请日：2009-10-14

    申请人： Yueh-Liang Hsu ,  Chi-Wen Chang

    发明人： Yueh-Liang Hsu ,  Chi-Wen Chang

    IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/31

    CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A quad flat non-leaded package including a leadframe, a chip, a plurality of first bonding wires and a molding compound is provided. The leadframe includes a plurality of first leads, and each first lead has a first portion and a second portion that extend along an axis. The length of the first portion is greater than the length of the second portion. The thickness of the first portion is greater than the thickness of the second portion. The chip is disposed on the leadframe and covers a portion of the first portions. The first bonding wires are connected between the chip and another portion of the first portions or the chip and the second portions, such that the chip is electrically connected to the first leads through the first bonding wires. The molding compound encapsulates a portion of the first leads, the chip and the first bonding wires.

    摘要翻译： 提供了包括引线框架，芯片，多个第一接合线和模制化合物的四边形扁平非引线封装。 引线框架包括多个第一引线，并且每个第一引线具有沿轴线延伸的第一部分和第二部分。 第一部分的长度大于第二部分的长度。 第一部分的厚度大于第二部分的厚度。 芯片设置在引线框架上并覆盖第一部分的一部分。 第一接合线连接在芯片与第一部分的另一部分或芯片和第二部分之间，使得芯片通过第一接合线电连接到第一引线。 模制化合物封装了第一引线，芯片和第一接合线的一部分。

    IMAGING SYSTEMS WITH FIXED OUTPUT SIZES AND FRAME RATES
    7.
    发明申请
    IMAGING SYSTEMS WITH FIXED OUTPUT SIZES AND FRAME RATES 有权
    具有固定输出尺寸和框架速率的成像系统

    公开(公告)号：US20120044375A1

    公开(公告)日：2012-02-23

    申请号：US12861760

    申请日：2010-08-23

    申请人： Sheng Lin ,  Adam Zerwick ,  Kai Yau Mok ,  Chi-Wen Chang

    发明人： Sheng Lin ,  Adam Zerwick ,  Kai Yau Mok ,  Chi-Wen Chang

    IPC分类号： H04N5/225 ,  G06K9/36

    CPC分类号： H04N19/188 ,  H04N19/146 ,  H04N19/625 ,  H04N19/68

    摘要： An imaging system may include an image sensor and an image encoder that encodes images from the image sensor with fixed output sizes and frame rates. The image encoder may encode images from the image sensor into an image format such as a Joint Photographic Experts Group (JPEG) format. The image encoder may insert padding data between image blocks in the encoded data to compensate in real time for variations in the encoded size of an image. The amount of padding data inserted by the encoder may be calculated to ensure the encoded image has a file size close to, but not greater than, the required fixed output size. If needed, the encoder may add additional padding data after the image blocks are encoded in a blanking period before a subsequent image is encoded so that the final size of the encoded image is equal to the required output size.

    摘要翻译： 成像系统可以包括图像传感器和图像编码器，其以固定的输出尺寸和帧速率对来自图像传感器的图像进行编码。 图像编码器可以将来自图像传感器的图像编码成诸如联合图像专家组（JPEG）格式的图像格式。 图像编码器可以在编码数据中的图像块之间插入填充数据，以实时补偿图像的编码大小的变化。 可以计算由编码器插入的填充数据的量，以确保编码图像的文件大小接近但不大于所需的固定输出大小。 如果需要，编码器可以在对后续图像进行编码之前在消隐期间对图像块进行编码之后添加附加填充数据，使得编码图像的最终尺寸等于所需的输出尺寸。

    Multi-bit image edge enhancement method and apparatus
    8.
    发明授权
    Multi-bit image edge enhancement method and apparatus 失效
    多位图像边缘增强方法和装置

    公开(公告)号：US5396584A

    公开(公告)日：1995-03-07

    申请号：US892062

    申请日：1992-05-29

    申请人： Tse-Han Lee ,  Ling-Yi Liu ,  Che-Hung Hu ,  Chi-Wen Chang

    发明人： Tse-Han Lee ,  Ling-Yi Liu ,  Che-Hung Hu ,  Chi-Wen Chang

    IPC分类号： G06T5/00 ,  G06F15/62

    CPC分类号： G06T7/0083 ,  G06T2207/10016 ,  G06T2207/20192

    摘要： Multi-bit image edge enhancement method and apparatus wherein a group of gradient mask matrices are applied to a "current matrix", wherein a TBAP (To Be Adjusted Pixel) is surrounded by neighboring pixels, to determine if the TBAP is at a location where a change of brightness occurs. From this matrix operation, a conclusion is derived as to the existence or non-existence of an edge and the direction of the brightness change. The current matrix and a predetermined number of previously evaluated and yet to be evaluated pixels are then compared to a set of reference bit patterns which depict possible segment changes to be corrected. If the result indicates that the TBAP is on an edge of a changing edge segment, a corresponding code will be generated to modify the TBAP to enhance the smoothness of a segment transition. In the case of an electrophotographic or a gray scale printing machine, the specific code will change either the location or the size of the TBAP; whereas in the case of a monochrome screen display, the specific code will change the intensity of the TBAP.

    摘要翻译： 多位图像边缘增强方法和装置，其中将一组梯度掩模矩阵应用于“当前矩阵”，其中TBAP（待调整像素）被相邻像素包围，以确定TBAP是否在 亮度发生变化。 从该矩阵运算得出关于边缘的存在或不存在以及亮度变化的方向的结论。 然后将当前矩阵和预定数量的先前评估且尚待评估的像素与一组参考位模式进行比较，该组参考位模式描绘了要校正的可能段变化。 如果结果表明TBAP位于边沿段的边缘，则将生成相应的代码来修改TBAP以提高段转换的平滑度。 在电子照相或灰度打印机的情况下，具体代码将改变TBAP的位置或大小; 而在单色屏幕显示的情况下，具体代码将改变TBAP的强度。