公开(公告)号：US08705297B2

公开(公告)日：2014-04-22

申请号：US13282830

申请日：2011-10-27

申请人： Sua Kim ,  Chul-woo Park ,  Hong-sun Hwang ,  Hak-soo Yu

发明人： Sua Kim ,  Chul-woo Park ,  Hong-sun Hwang ,  Hak-soo Yu

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/06 ,  G11C2207/002 ,  G11C2207/005

摘要： A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal.

摘要翻译： 半导体存储器件包括至少一个存储单元块和至少一个连接单元。 所述至少一个存储单元块具有包括连接到第一位线的至少一个第一存储单元的第一区域和包括连接到第二位线的至少一个第二存储器单元的第二区域。 所述至少一个连接单元被配置为基于第一控制信号选择性地将第一位线连接到对应的位线读出放大器，并且被配置为经由对应的全局位选择性地将第二位线连接到对应的位线读出放大器 基于第二控制信号。

公开(公告)号：US08553484B2

公开(公告)日：2013-10-08

申请号：US13238553

申请日：2011-09-21

申请人： Sua Kim ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

发明人： Sua Kim ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/4099

摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.

摘要翻译： 半导体存储器件包括存储单元和第一参考存储单元。 存储单元包括第一开关元件和用于存储数据的第一电容器。 第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。 第一电容器具有用于接收第一板电压的第二端子。 第一参考存储单元包括第一参考开关元件和第一电容器。 第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。 第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

公开(公告)号：US08987811B2

公开(公告)日：2015-03-24

申请号：US13588513

申请日：2012-08-17

申请人： Hak-soo Yu ,  Chulwoo Park ,  Hyun-Woo Chung ,  Sua Kim ,  Hyunho Choi ,  Hongsun Hwang

发明人： Hak-soo Yu ,  Chulwoo Park ,  Hyun-Woo Chung ,  Sua Kim ,  Hyunho Choi ,  Hongsun Hwang

IPC分类号： H01L29/66 ,  H01L27/108

CPC分类号： H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

摘要： According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.

摘要翻译： 根据示例性实施例，半导体器件包括从衬底突出的多个有源柱。 每个有源支柱包括上和下掺杂区之间的沟道区。 接触栅电极面对沟道区并连接到字线。 字线在第一方向延伸。 位线连接到下掺杂区域并沿第二方向延伸。 该半导体器件还包括连接多个有源支柱的至少两个相邻有效支柱的沟道区域的串体连接部分。

公开(公告)号：US08809926B2

公开(公告)日：2014-08-19

申请号：US13605275

申请日：2012-09-06

申请人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

发明人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

IPC分类号： H01L21/02

CPC分类号： H01L27/101 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/228

摘要： A semiconductor memory device may include a common source region on a substrate, an active pattern between the substrate and the common source region, a gate pattern facing a sidewall of the active pattern, a gate dielectric pattern between the gate pattern and the active pattern, a variable resistance pattern between the common source region and the active pattern, and an interconnection line.

摘要翻译： 半导体存储器件可以包括衬底上的公共源极区域，衬底和公共源极区域之间的有源图案，面对有源图案的侧壁的栅极图案，栅极图案和有源图案之间的栅极电介质图案， 公共源极区域和有源图案之间的可变电阻图案以及互连线。

公开(公告)号：US20150067248A1

公开(公告)日：2015-03-05

申请号：US14465105

申请日：2014-08-21

申请人： Jun Hee Yoo ,  Sung Hyun Lee ,  Dongsoo Kang ,  Sua Kim ,  Haksoo Yu ,  Jaeyoun Youn ,  Hyojin Choi

发明人： Jun Hee Yoo ,  Sung Hyun Lee ,  Dongsoo Kang ,  Sua Kim ,  Haksoo Yu ,  Jaeyoun Youn ,  Hyojin Choi

IPC分类号： G06F12/10

CPC分类号： G06F11/00 ,  G11C8/06 ,  G11C11/401 ,  G11C29/78 ,  G11C2029/4402

摘要： A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.

摘要翻译： 提供了不良页面管理系统以保证诸如DRAM之类的易失性半导体存储器件的产量。 DRAM中存在不良页面列表。 存储器控制器中的页面重新映射器与调度单元的正常操作并行执行页面重映射操作，以执行延迟开销隐藏功能。 DRAM的芯片尺寸减小或最小化。 DRAM控制器执行延迟开销隐藏功能来控制DRAM。

公开(公告)号：US08816432B2

公开(公告)日：2014-08-26

申请号：US13586018

申请日：2012-08-15

申请人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park

发明人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park

IPC分类号： H01L29/66

CPC分类号： H01L27/10876 ,  H01L27/10885 ,  H01L27/228 ,  H01L27/2454

摘要： Semiconductor devices having vertical channel transistors are provided. The semiconductor device includes an insulation layer on a substrate and a buried bit line on the insulation layer. The buried bit line extends in a first direction. An active pillar is disposed on the buried bit line. The active pillar includes a lower dopant region, a channel region having a first sidewall and an upper dopant region vertically stacked on the buried bit line. A contact gate electrode is disposed to be adjacent to the first sidewall of the channel region. A word line is electrically connected to the contact gate electrode. The word line extends in a second direction intersecting the first direction. A string body connector is electrically connected to the channel region. Related methods are also provided.

摘要翻译： 提供具有垂直沟道晶体管的半导体器件。 半导体器件包括衬底上的绝缘层和绝缘层上的掩埋位线。 埋置的位线沿第一方向延伸。 有源柱设置在掩埋位线上。 有源柱包括下掺杂区域，具有垂直堆叠在掩埋位线上的第一侧壁和上掺杂区的沟道区。 接触栅电极设置成与沟道区的第一侧壁相邻。 字线电连接到接触栅电极。 字线在与第一方向相交的第二方向上延伸。 弦体连接器电连接到通道区域。 还提供了相关方法。

公开(公告)号：US20130056812A1

公开(公告)日：2013-03-07

申请号：US13605275

申请日：2012-09-06

申请人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

发明人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

IPC分类号： H01L29/82

CPC分类号： H01L27/101 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/228

摘要： A semiconductor memory device may include a common source region on a substrate, an active pattern between the substrate and the common source region, a gate pattern facing a sidewall of the active pattern, a gate dielectric pattern between the gate pattern and the active pattern, a variable resistance pattern between the common source region and the active pattern, and an interconnection line.

摘要翻译： 半导体存储器件可以包括衬底上的公共源极区域，衬底和公共源极区域之间的有源图案，面对有源图案的侧壁的栅极图案，栅极图案和有源图案之间的栅极电介质图案， 公共源极区域和有源图案之间的可变电阻图案以及互连线。