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公开(公告)号：US20070036012A1
公开(公告)日：2007-02-15
申请号：US11191709
申请日：2005-07-28
申请人： Sudhir Madan , Bryan Sheffield
发明人： Sudhir Madan , Bryan Sheffield
IPC分类号： G11C7/00
摘要： An amplifier circuit and method is disclosed. The amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706,708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726). The control gates of the first and second pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.
摘要翻译： 公开了放大器电路和方法。 放大器电路包括放大器部分（700），均衡部分（770）和激活部分（720）。 放大器部分的P沟道晶体管（702,704）耦合到电源端子（802）。 放大器部分的N沟道晶体管（706,708）分别耦合在P沟道晶体管和第一和第二输入端（760,762）之间。 在激活部分中，第一和第二下拉晶体管（722,724）分别耦合在第一和第二输入端子与第二电源端子（726）之间。 第一和第二下拉晶体管的控制栅极彼此耦合。 在操作中，施加到第一和第二输入端的电压信号被N沟道晶体管放大。 然后施加控制信号以将第一和第二输入端耦合到电源电压。
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公开(公告)号：US07095671B2
公开(公告)日：2006-08-22
申请号：US11121387
申请日：2005-05-03
IPC分类号： G11C7/00
CPC分类号： G11C29/027 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.
摘要翻译： 电气保险丝（eFuse）被应用于存储器性能调整的任务，以通过不需要额外的处理步骤和昂贵的设备来改进早期保险丝技术。 标准电熔丝（eFuse）硬件链提供了软测试功能，其中可以在实际编程保险丝之前测试存储器减速的影响。 因此，电熔丝提供非常有效的非易失性方法，以通过存储器修整来匹配逻辑存储器接口，大大降低成本和所涉及的周期时间。
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公开(公告)号：US20050036385A1
公开(公告)日：2005-02-17
申请号：US10945725
申请日：2004-09-21
申请人： Xiaowei Deng , Theodore Houston , Bryan Sheffield
发明人： Xiaowei Deng , Theodore Houston , Bryan Sheffield
IPC分类号： G11C8/08 , G11C11/417 , G11C11/34
CPC分类号： G11C8/08 , G11C11/417
摘要： The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.
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公开(公告)号：US06909301B2
公开(公告)日：2005-06-21
申请号：US10236328
申请日：2002-09-06
CPC分类号： G11C29/50012 , G01R31/3016 , G11C29/14 , G11C29/50
摘要： An embodiment of the invention is a method for measuring access time where the frequency of a ring oscillator is measured with and without a device under test 1 in the ring. Those two frequencies are compared to calculate the access time of the device under test 1. Another embodiment of the invention is circuitry 25 that measures the frequency of a ring oscillator with and without a device under test 1. Again the two frequencies are compared to calculate the access time of the device under test 1.
摘要翻译： 本发明的一个实施例是一种测量接入时间的方法，其中测量环路振荡器的频率是否具有环中的被测器件1。 比较这两个频率来计算被测设备1的访问时间。 本发明的另一实施例是测量具有和不具有被测器件1的环形振荡器的频率的电路25。 将两个频率再次进行比较，以计算被测器件1的访问时间。
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公开(公告)号：US08570068B2
公开(公告)日：2013-10-29
申请号：US12768899
申请日：2010-04-28
IPC分类号： H03K19/0175
CPC分类号： H03K19/01855 , H03K3/012 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H03K19/0963
摘要： A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.
摘要翻译： 电路包括逻辑门驱动器的操作PMOS晶体管。 控制电路被配置为在待机模式期间关闭操作PMOS晶体管。 电路还包括耦合到输出节点的牺牲PMOS晶体管。 操作PMOS晶体管耦合到输出节点。 牺牲PMOS晶体管被配置为在待机模式期间将输出节点保持在逻辑1。
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公开(公告)号：US20070081379A1
公开(公告)日：2007-04-12
申请号：US11234346
申请日：2005-09-23
申请人： Michael Clinton , Stephen Heinrich-Barna , Theodore Houston , George Jamison , Kun-hsi Li , Jonathon Miller , Bryan Sheffield
发明人： Michael Clinton , Stephen Heinrich-Barna , Theodore Houston , George Jamison , Kun-hsi Li , Jonathon Miller , Bryan Sheffield
IPC分类号： G11C11/24
CPC分类号： G11C11/419
摘要： One embodiment provides a system to assist setting a state of a latch system. The system includes a latch system connected to a node, the latch system residing in one of a first state and a second state. A charge storage device is coupled to maintain the node at a first voltage according to an amount of stored charge. A write assist system is connected between the node and a second voltage. The write assist network is configured, when the node is selected, to discharge the charge storage device and to pull the node from the first voltage to a discharge voltage that is outside a range defined by the first voltage and the second voltage to facilitate setting the latch system to another of the first state and the second state.
摘要翻译： 一个实施例提供一种帮助设置闩锁系统的状态的系统。 系统包括连接到节点的锁存系统，锁存系统驻留在第一状态和第二状态之一中。 电荷存储装置被耦合以根据存储的电荷的量将节点维持在第一电压。 写入辅助系统连接在节点和第二电压之间。 写入辅助网络被配置为当选择节点时，放电电荷存储装置并且将节点从第一电压拉到超出由第一电压和第二电压限定的范围的放电电压，以便于设置 将系统锁定到第一状态和第二状态中的另一状态。
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公开(公告)号：US20070023859A1
公开(公告)日：2007-02-01
申请号：US11192825
申请日：2005-07-29
申请人： Robert Pitts , Bryan Sheffield , Roger Griesmer , Joe McPherson
发明人： Robert Pitts , Bryan Sheffield , Roger Griesmer , Joe McPherson
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.
摘要翻译： 本发明提供了一种半导体器件熔丝，其包括金属层和将金属层电耦合到熔丝层的第一半导体层，其中熔丝层与金属层间隔开。 半导体器件熔丝进一步包括形成与熔丝层的熔结接口的第二半导体层。 当预定义的功率通过第二半导体层透射到熔丝层时，该熔接结界面被配置为形成开路。
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公开(公告)号：US20050024960A1
公开(公告)日：2005-02-03
申请号：US10630963
申请日：2003-07-30
CPC分类号： G11C29/027 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.
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公开(公告)号：US07376871B2
公开(公告)日：2008-05-20
申请号：US10635348
申请日：2003-08-06
IPC分类号： G01R31/28
CPC分类号： G11C29/12015 , G11C15/00 , G11C29/02 , G11C29/24
摘要： Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes. Accordingly, the CAM can be debugged to isolate memory failures from priority encoder failures, which significantly reduces the need for design changes. The present invention provides the ability to test the CAM functions very efficiently, thereby reducing the test time.
摘要翻译： 通过使用各种测试模式，即使存储器有缺陷，也能够实现CAM专用电路测试的配置和方法。 因此，CAM可以进行调试，以将存储器故障与优先编码器故障隔离开来，这显着地减少了对设计变更的需求。 本发明提供了非常有效地测试CAM功能的能力，从而减少测试时间。
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公开(公告)号：US06928011B2
公开(公告)日：2005-08-09
申请号：US10630963
申请日：2003-07-30
CPC分类号： G11C29/027 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.
摘要翻译： 电气保险丝（eFuse）被应用于存储器性能调整的任务，以通过不需要额外的处理步骤和昂贵的设备来改进早期保险丝技术。 标准电熔丝（eFuse）硬件链提供了软测试功能，其中可以在实际编程保险丝之前测试存储器减速的影响。 因此，电熔丝提供非常有效的非易失性方法，以通过存储器修整来匹配逻辑存储器接口，大大降低成本和所涉及的周期时间。
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