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16 条记录 (耗时 0.025 秒)

    Wiring CAD apparatus
    5.
    发明授权
    Wiring CAD apparatus 失效
    接线CAD设备

    公开(公告)号：US5642286A

    公开(公告)日：1997-06-24

    申请号：US497550

    申请日：1995-06-30

    申请人： Ryoji Yamada ,  Masaharu Nishimura ,  Yasuhiro Yamashita ,  Kazuyuki Iida

    发明人： Ryoji Yamada ,  Masaharu Nishimura ,  Yasuhiro Yamashita ,  Kazuyuki Iida

    IPC分类号： H01L21/82 ,  G06F17/50 ,  G06F19/00

    CPC分类号： G06F17/5077

    摘要： A wiring CAD apparatus wherein a situation of a noticed event can be identified at a moment on a screen. The wiring CAD apparatus comprises a searching timing detection section for detecting a new displaying processing/deletion processing timing as a searching timing for a non-wired pin, a non-wired pin searching section operable in response to the searching timing detected by said searching timing detection section for searching the non-wired pin, and a display data production section for producing display data in accordance with which the non-wired pin searched out by said non-wired pin searching section is to be displayed on a display section in a visually distinguishable condition from another already wired part pin. The display data produced by said display data production section is displayed on the display section under the control of a displaying control section. The wiring CAD apparatus can be applied to a CAD system with which wiring designing for an LSI, an MCM, a PWB or the like can be performed interactively.

    摘要翻译： 一种布线CAD装置，其中可以在屏幕上的某一时刻识别注意事件的情况。 布线CAD装置包括搜索定时检测部分，用于检测新的显示处理/删除处理定时作为非有线引脚的搜索定时;无线引脚搜索部分，其可响应于由所述搜索定时检测到的搜索定时操作 用于搜索非有线引脚的检测部分和用于产生显示数据的显示数据产生部分，根据该显示数据，由所述非有线引脚搜索部分搜索出的非有线引脚将在视觉上显示在显示部分上 可区分条件与另一已经有线的部分引脚。 在显示控制部分的控制下，由显示数据产生部分产生的显示数据显示在显示部分上。 布线CAD装置可以应用于可以交互地执行用于LSI，MCM，PWB等的布线设计的CAD系统。

    Apparatus, method and program for supporting designing of integrated circuit using a common format
    6.
    发明授权
    Apparatus, method and program for supporting designing of integrated circuit using a common format 有权
    使用通用格式支持集成电路设计的装置，方法和程序

    公开(公告)号：US07444612B2

    公开(公告)日：2008-10-28

    申请号：US11016988

    申请日：2004-12-21

    申请人： Masato Ariyama ,  Junko Taira ,  Kazuyuki Iida ,  Minoru Yabumoto ,  Tomohisa Suzuki ,  Minako Kubota

    发明人： Masato Ariyama ,  Junko Taira ,  Kazuyuki Iida ,  Minoru Yabumoto ,  Tomohisa Suzuki ,  Minako Kubota

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： In designing integrated circuits such as FPGAs, a design support environment including the quality of design data is improved and the design efficiency is improved. An integrated-circuit design support apparatus that supports designing of an integrated circuit having a plurality of pins is provided. The apparatus includes a processor (a central processing unit) that forms a pin layout matrix (a matrix sheet) by unifying pin layout information of the integrated circuit using a common format and arranging the pin layout information in coordinates. The processor creates an integrated-circuit design library from the pin layout matrix.

    摘要翻译： 在设计FPGA等集成电路时，提高了设计数据质量的设计支持环境，提高了设计效率。 提供一种支持具有多个引脚的集成电路的设计的集成电路设计支持装置。 该装置包括通过使用公共格式统一集成电路的引脚布局信息并且将引脚布局信息布置在坐标中来形成引脚布局矩阵（矩阵）的处理器（中央处理单元）。 处理器从引脚布局矩阵创建集成电路设计库。

    Wiring device and wiring method
    7.
    发明授权
    Wiring device and wiring method 失效
    接线装置及接线方式

    公开(公告)号：US5867810A

    公开(公告)日：1999-02-02

    申请号：US739751

    申请日：1996-10-29

    申请人： Hiroshi Miura ,  Yasuhiro Yamashita ,  Kazuyuki Iida ,  Ryoji Yamada ,  Yumiko Katsuyama

    发明人： Hiroshi Miura ,  Yasuhiro Yamashita ,  Kazuyuki Iida ,  Ryoji Yamada ,  Yumiko Katsuyama

    IPC分类号： G06F19/00

    CPC分类号： G06F19/00

    摘要： A wiring device and wiring method suitable for designing LSIs or printed boards or the like. The wiring device includes a wiring pattern editing unit for editing wiring patterns; a noise analyzing unit for analyzing a noise occurring when a circuit is operated according to the wiring patterns edited by the wiring editing unit; and a noise occurring spot specifying unit for specifying a spot when noise occurs in the wiring pattern, based on the solution analyzed by the noise analyzing unit and the wiring pattern edited in the wiring pattern editing unit The man-hours of an operator can be reduced by interlocking the crosstalk noise analysis with the wiring pattern editing function and then by reducing the number of man-hours needed to correct a wiring pattern by an operator.

    摘要翻译： 适用于设计LSI或印刷电路板等的布线装置和布线方法。 布线装置包括用于编辑布线图案的布线图案编辑单元; 噪声分析单元，用于根据由布线编辑单元编辑的布线图案来分析当电路工作时发生的噪声; 以及噪声发生点指定单元，其基于由噪声分析单元分析的解和在布线图案编辑单元中编辑的布线图案，在布线图案中发生噪声时指定点。可以减少操作者的工时 通过将串扰噪声分析与布线图案编辑功能互锁，然后通过减少操作者校正布线图案所需的工时数量。

    Reversible heat-sensitive recording material
    8.
    发明授权
    Reversible heat-sensitive recording material 失效
    可逆热敏记录材料

    公开(公告)号：US5395815A

    公开(公告)日：1995-03-07

    申请号：US74124

    申请日：1993-06-08

    申请人： Mitsuhiro Ikeda ,  Yasuro Yokota ,  Shigetoshi Hiraishi ,  Kazuyuki Iida ,  Hidekazu Sano

    发明人： Mitsuhiro Ikeda ,  Yasuro Yokota ,  Shigetoshi Hiraishi ,  Kazuyuki Iida ,  Hidekazu Sano

    IPC分类号： B41M5/337 ,  B41M5/30 ,  B41M5/333

    CPC分类号： B41M5/3335 ,  B41M5/3336

    摘要： As a reversible heat-sensitive recording material which contains a normally colorless or palely colored electron donating dye precursor and an electron accepting compound capable of causing said dye precursor to change reversibly in color density due to the difference in cooling rate after heating, one in which images can be formed and erased with good contrast and images high in time stability can be maintained under environment of everyday life can be obtained by using a phenolic compound having at least one aliphatic hydrocarbon group of 6 or more carbon atoms as the said electron donating compound.

    摘要翻译： 作为可逆热敏记录材料，其包含通常无色或浅色电子供体染料前体和能够使得所述染料前体由于加热后的冷却速度差而在颜色密度上可逆地改变的电子接受性化合物，其中 可以形成和擦除图像，具有良好的对比度，并且通过使用具有至少一个具有6个或更多个碳原子的脂肪族烃基的酚类化合物作为所述给电子化合物，可以在日常生活环境下保持高度稳定的稳定性图像 。

    Semiconductor circuit element device with arrangement for testing the device and method of test
    9.
    发明授权
    Semiconductor circuit element device with arrangement for testing the device and method of test 失效
    具有用于测试装置和测试方法的装置的半导体电路元件装置

    公开(公告)号：US5565766A

    公开(公告)日：1996-10-15

    申请号：US952651

    申请日：1992-09-28

    申请人： Hiroichi Kuwahara ,  Kiyoyuki Yoshida ,  Kazuyuki Iida

    发明人： Hiroichi Kuwahara ,  Kiyoyuki Yoshida ,  Kazuyuki Iida

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G01R31/02 ,  G06F11/22

    CPC分类号： G01R31/318505

    摘要： A semiconductor circuit element device with an arrangement for testing the device including a plurality of first logic circuits provided in correspondence with internal line groups which are formed by grouping the internal lines into a plurality of groups, a plurality of internal lines belonging to a group in question constituting the input lines of the plurality of first logic circuits, for outputting an active output signal when all of the inputs represent active signals and outputting an inactive output signal when at least one of the inputs represents an inactive signal; and a second logic circuit constituted by one or more stages of circuit structures, for receiving the outputs of the first logic circuits and sending out an output signal such that the output signal in the case where all of the inputs are inactive output signals is different from the output signal in the case where at least one of the inputs is an active output signal.

    摘要翻译： 一种具有用于测试该装置的装置的半导体电路元件装置，包括与通过将内部线分组成多个组而形成的内部线路组相对应地设置的多个第一逻辑电路，属于一组中的组的多条内线 构成多个第一逻辑电路的输入线的问题，用于当所有输入表示有源信号时输出有效输出信号，并且当至少一个输入表示无效信号时输出无效输出信号; 以及由一个或多个电路结构级构成的第二逻辑电路，用于接收第一逻辑电路的输出并发出输出信号，使得在所有输入为非活动输出信号的情况下，输出信号不同于 在至少一个输入是有源输出信号的情况下的输出信号。