公开(公告)号：US06289046B1

公开(公告)日：2001-09-11

申请号：US09119006

申请日：1998-07-20

申请人： Sumitaka Takeuchi ,  Shuji Murakami ,  Hiroshi Ochi ,  Ken Onaga

发明人： Sumitaka Takeuchi ,  Shuji Murakami ,  Hiroshi Ochi ,  Ken Onaga

IPC分类号： H03H730

CPC分类号： H04L25/03038 ,  H03H21/0012 ,  H04L25/03076

摘要： An adaptive equalization method updates the tap coefficient through utilization of the mean value of instantaneous gradient vectors, thereby ensuring the likelihood of pseudo transmission data that is generated from received data.

摘要翻译： 自适应均衡方法通过利用瞬时梯度向量的平均值来更新抽头系数，从而确保从接收数据生成的伪传输数据的可能性。

公开(公告)号：US5376915A

公开(公告)日：1994-12-27

申请号：US43710

申请日：1993-04-08

申请人： Sumitaka Takeuchi ,  Masao Ito

发明人： Sumitaka Takeuchi ,  Masao Ito

IPC分类号： G06F7/02

CPC分类号： G06F7/026

摘要： Disclosed is an absolute value comparator for comparing respective absolute values of sequentially applied two data. A decoder circuit sequentially converts the applied data into a plurality of bit signals in accordance with a predetermined rule. After a preceding conversion bit signal is once held in a register circuit, the held bit signal is inverted for each bit by an inversion circuit. Thus, a logic circuit receives a preceding inverted bit signal and a succeeding conversion bit signal and outputs an output signal B indicating the result of comparison. Since a full adder is unnecessary, a comparison between the absolute values of the applied data can be made at a high speed.

摘要翻译： 公开了一种用于比较顺序应用的两个数据的绝对值的绝对值比较器。 解码器电路根据预定规则顺序地将所施加的数据转换成多个比特信号。 在先前的转换位信号一旦被保持在寄存器电路中之后，所保持的位信号通过反相电路针对每个位反相。 因此，逻辑电路接收先前的反相位信号和后续转换位信号，并输出表示比较结果的输出信号B. 由于不需要全加器，所以可以高速地进行应用数据的绝对值之间的比较。

公开(公告)号：US4982354A

公开(公告)日：1991-01-01

申请号：US204956

申请日：1988-05-31

申请人： Sumitaka Takeuchi ,  Keisuke Okada

发明人： Sumitaka Takeuchi ,  Keisuke Okada

IPC分类号： G06F7/60 ,  H03H17/02 ,  H03H17/06

CPC分类号： H03H17/06 ,  H03H17/0223

摘要： An input analogue signal is converted to a two-valued signal and then it is supplied to each encoder. Each gate signal forming circuit forms a gate signal based on an input digital signal. Each encoder encodes the above stated two-valued signal, an encoding function thereof being determined based on the above stated gate signal. As a result, each encoder outputs a result of multiplication of the two-valued signal and the digital signal in the form of a binary digital signal.

摘要翻译： 输入模拟信号被转换为二值信号，然后提供给每个编码器。 每个门信号形成电路基于输入数字信号形成门信号。 每个编码器对上述两值信号进行编码，其编码功能基于上述门信号确定。 结果，每个编码器输出二值数字信号形式的二值信号和数字信号的相乘结果。

公开(公告)号：US5253194A

公开(公告)日：1993-10-12

申请号：US866708

申请日：1992-04-10

申请人： Sumitaka Takeuchi ,  Keisuke Okada

发明人： Sumitaka Takeuchi ,  Keisuke Okada

IPC分类号： G06F7/533 ,  G06F7/52 ,  G06F7/523 ,  G06F7/53

CPC分类号： G06F7/53

摘要： A decode circuit decodes digital signals X1 and X0 as multiplicand to output decoded signals A0-A3. One of these decoded signals A3-A0 is set to be logic 1 in accordance with a value of a multiplicand. A logical operation circuit includes a plurality of operation circuits. Each logical operation circuit performs an independent operation for obtaining a logical value of each bit of the digital signal which is a multiplication result, based on the decoded signals A0-A3 and the digital signals R1 and R0 as a multiplier. Therefore, a result of an operation of a certain bit does not affect results of operations of other bits, so that the logical operation of each bit can be conducted without waiting termination of the logical operations of other bits, which enables high-speed multiplications.

摘要翻译： 解码电路将数字信号X1和X0解码为被乘数，以输出解码信号A​​0-A3。 根据被乘数的值将这些解码信号A​​3-A0中的一个设置为逻辑1。 逻辑运算电路包括多个运算电路。 每个逻辑运算电路基于解码信号A​​0-A3和数字信号R1和R0作为乘法器执行用于获得作为乘法结果的数字信号的每个比特的逻辑值的独立操作。 因此，某位的操作结果不影响其他位的操作结果，从而可以在不等待终止其他位的逻辑运算的情况下进行每个位的逻辑运算，从而实现高速乘法运算。

公开(公告)号：US4947173A

公开(公告)日：1990-08-07

申请号：US241877

申请日：1988-09-08

申请人： Keisuki Okada ,  Sumitaka Takeuchi ,  Masatoshi Kimura

发明人： Keisuki Okada ,  Sumitaka Takeuchi ,  Masatoshi Kimura

IPC分类号： H03M1/36 ,  G06J1/00

CPC分类号： G06J1/00

摘要： First and second comparator groups compare first and second analogue signals applied thereto, respectively, with reference voltages and convert the results of the comparison to binary signals to output the binary signals to an encoding circuit. The encoding circuit converts the binary signals supplied from the first and second comparator groups to digital data of a binary code corresponding to the product of the first and second analogue signals to output the digital data.

摘要翻译： 第一和第二比较器组分别将施加到其上的第一和第二模拟信号与参考电压进行比较，并将比较结果转换为二进制信号，以将二进制信号输出到编码电路。 编码电路将从第一和第二比较器组提供的二进制信号转换为对应于第一和第二模拟信号的乘积的二进制码的数字数据，以输出数字数据。

公开(公告)号：US5781462A

公开(公告)日：1998-07-14

申请号：US530580

申请日：1995-09-19

申请人： Kazuya Yamanaka ,  Sumitaka Takeuchi

发明人： Kazuya Yamanaka ,  Sumitaka Takeuchi

IPC分类号： G06F7/53 ,  G06F7/52 ,  G06F7/533 ,  G06F17/10 ,  H03H17/02

CPC分类号： G06F7/5338

摘要： It is an object of the present invention to simplify a multiplier so as to reduce the circuit scale of a digital filter which uses a large number of multipliers. Outputs of a Booth decoder 4 are stored in registers 5.sub.1 -5.sub.(n+1)/2 provided corresponding to partial product generating circuits 106.sub.1 -106.sub.(n+1)2. By providing control signals from the registers 5.sub.1 -5.sub.(n+1)/2 to the partial product generating circuits 106.sub.1 -106.sub.(n+1)/2, the Booth decoder 4 is made common. The number of Booth decoders which have conventionally been provided in a one-to-one correspondence with the partial product generating circuits can be reduced to one and the multiplier can be simplified.

摘要翻译： 本发明的目的是简化乘法器，以减少使用大量乘法器的数字滤波器的电路规模。 展位解码器4的输出被存储在对应于部分积产生电路1061-106（n + 1）2的寄存器51-5（n + 1）/ 2中。 通过从寄存器51-5（n + 1）/ 2向部分乘积产生电路1061-106（n + 1）/ 2提供控制信号，布斯解码器4是公共的。 传统上与部分积产生电路一一对应地提供的布斯解码器的数量可以减少到1个，乘法器可以简化。

公开(公告)号：US5216424A

公开(公告)日：1993-06-01

申请号：US707145

申请日：1991-05-31

申请人： Hiroyuki Kouno ,  Sumitaka Takeuchi ,  Keisuke Okada

发明人： Hiroyuki Kouno ,  Sumitaka Takeuchi ,  Keisuke Okada

IPC分类号： G06F7/38 ,  G06F7/48 ,  H03M7/04

CPC分类号： H03M7/04 ,  G06F7/48

摘要： A binary data converter is adapted to convert a positive binary data into a negative binary data represented by a complement on two and vice verse. The conversion is effected as follows. A least significant bit of an inputted binary data is outputted as the least significant bit of the converted binary date as it is. With respect to bit signal other than the least significant bit, respective input bit signals less significant than the corresponding input bit signal are ORed. Depending on the result thereof, inverted or non-inverted signals of the corresponding input bit signals are outputted as the bit signals of the converted binary data. Therefore, carry delay is not generated, and thus the operation speed can be increased. Further, the simple circuit structures can reduce the number of required elements.

摘要翻译： 二进制数据转换器适于将正二进制数据转换成由二进制补码表示的负二进制数据。 转换如下进行。 输入的二进制数据的最低有效位作为转换的二进制日期的最低有效位被原样输出。 对于除了最低有效位之外的位信号，相对于相应的输入位信号而言，相对于输入位信号的有效值为“或”。 根据其结果，相应的输入位信号的反相或非反转信号作为转换的二进制数据的位信号被输出。 因此，不产生进位延迟，能够提高运转速度。 此外，简单的电路结构可以减少所需元件的数量。

公开(公告)号：US4903027A

公开(公告)日：1990-02-20

申请号：US159405

申请日：1988-02-11

申请人： Sumitaka Takeuchi ,  Keisuke Okada

发明人： Sumitaka Takeuchi ,  Keisuke Okada

IPC分类号： H03M1/14 ,  G06J1/00 ,  H03M1/36

CPC分类号： G06J1/00 ,  H03M1/365

摘要： An A/D converter of a serial-parallel comparison type has both multiplying functions of an analog input data and a digital input data. The analog input data V.sub.X is converted into a digital code I.sub.c corresponding to two more significant digits, by a first parallel comparing portion and a first determining circuit, and converted into a digital code I.sub.f corresponding to two less significant digits by a second parallel comparing portion and a second determining circuit. The digital codes I.sub.c and I.sub.f are alternately applied to a control circuit by a first selector circuit. Two more significant bits R.sub.c and two less significant bits R.sub.f of a 4-bit digital input data are respectively applied to a control signal generating circuit by a second selector circuit. Multiplications of R.sub.c I.sub.c, RfIc, R.sub.c I.sub.f and R.sub.f I.sub.f are serially performed within the time period of one conversion by the control signal generating circuit and the control circuit. The multiplied results are shifted four bits, two bits, two bits and 0 bits, respectively, and then, added to each other. As a result, the product of the analogue input data and the digital input data is calculated.

摘要翻译： 并行比较型的A / D转换器具有模拟输入数据和数字输入数据的乘法功能。 通过第一并行比较部分和第一确定电路将模拟输入数据VX转换成对应于两个有效数字的数字代码Ic，并且被转换成数字代码如果对应于由第二并行比较部分的两个较低有效数字 和第二确定电路。 数字代码Ic和If由第一选择器电路交替地施加到控制电路。 4位数字输入数据的两个有效位Rc和两个较低有效位Rf由第二选择器电路分别施加到控制信号发生电路。 RcIc，RfIc，RcIf和RfIf的乘法在控制信号发生电路和控制电路的一次转换的时间段内连续执行。 相乘的结果分别移位四位，两位，两位和0位，然后相加。 结果，计算模拟输入数据和数字输入数据的乘积。

公开(公告)号：US4896284A

公开(公告)日：1990-01-23

申请号：US226636

申请日：1988-08-01

申请人： Sumitaka Takeuchi ,  Keisuke Okada ,  Masatoshi Kimura

发明人： Sumitaka Takeuchi ,  Keisuke Okada ,  Masatoshi Kimura

IPC分类号： H03M1/36 ,  G06F7/52 ,  G06J1/00

CPC分类号： G06J1/00 ,  G06F7/523 ,  H03M1/365

摘要： A semiconductor integrated circuit so arranged that selection is made out of output signals of a decision circuit which determines the levels of analog values inputted as an object for multiplication and multiplication is carried out with respect to the selected signal and the digital value inputted as an object for multiplication, the result of the multiplication being added with the digital value as shifted to the higher position of specified bits, a multiplication result being thereby calculated with respect to the analog value and the digital value, whereby the required area of wiring connections is reasonably reduced and faster operation is assured.

摘要翻译： 一种半导体集成电路，其被配置为根据所选择的信号和作为对象输入的数字值，执行确定作为乘法和乘法对象输入的模拟值的电平的判定电路的输出信号的选择 为了乘法，乘法的结果被加上移动到指定位的较高位置的数字值，由此相对于模拟值和数字值计算乘法结果，由此所需的接线连接面积是合理的 减少和更快的操作得到保证。

公开(公告)号：US5583502A

公开(公告)日：1996-12-10

申请号：US263429

申请日：1994-06-21

申请人： Sumitaka Takeuchi ,  Toshio Kumamoto

发明人： Sumitaka Takeuchi ,  Toshio Kumamoto

IPC分类号： H03M1/10 ,  H03M1/12 ,  H03M1/66

CPC分类号： H03M1/108 ,  H03M1/12 ,  H03M1/66

摘要： There is disclosed an A-D converter testing circuit wherein exclusive-OR gates (13a, 13b) provide the exclusive-OR of the high-order bits (D.sub.1a, D.sub.1b) of the outputs of A-D converters (12a, 12b) and the exclusive-OR of the high-order bits (D.sub.1b, D.sub.1c) of the outputs of A-D converters (12b, 12c), respectively, and an OR gate (13c) provides the logical sum of the outputs of the both gates, which is "L" if all of the bits (D.sub.1a, D.sub.1b, D.sub.1c) are equal. A tri-state buffer (15a) receives the output of the OR gate (13c) at its control end and receives the bit (D.sub.1c) at its input. When all of the A-D converters are normal, all of the bits (D.sub.1a, D.sub.1b, D.sub.1c) are equal and are applied to the output of the tri-state buffer (15a). When one or some of the A-D converters are abnormal, the output of the tri-state buffer (15a) enters a high-impedance state. The A-D converter testing circuit, therefore, rapidly judges whether the A-D converters are defective or non-defective.

摘要翻译： 公开了一种AD转换器测试电路，其中异或门（13a，13b）提供AD转换器（12a，12b）的输出的高位（D1a，D1b）和异或 分别为AD转换器（12b，12c）的输出的高位（D1b，D1c）和或门（13c）提供两个门的输出的逻辑和，如果 所有位（D1a，D1b，D1c）相等。 三态缓冲器（15a）在其控制端接收或门（13c）的输出，并在其输入端接收位（D1c）。 当所有A-D转换器都正常时，所有位（D1a，D1b，D1c）都相等，并被施加到三态缓冲器（15a）的输出。 当一个或一些A-D转换器异常时，三态缓冲器（15a）的输出进入高阻抗状态。 因此，A-D转换器测试电路快速判断A-D转换器是有缺陷的还是无缺陷的。