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公开(公告)号：US06289046B1
公开(公告)日：2001-09-11
申请号：US09119006
申请日：1998-07-20
申请人： Sumitaka Takeuchi , Shuji Murakami , Hiroshi Ochi , Ken Onaga
发明人： Sumitaka Takeuchi , Shuji Murakami , Hiroshi Ochi , Ken Onaga
IPC分类号： H03H730
CPC分类号： H04L25/03038 , H03H21/0012 , H04L25/03076
摘要： An adaptive equalization method updates the tap coefficient through utilization of the mean value of instantaneous gradient vectors, thereby ensuring the likelihood of pseudo transmission data that is generated from received data.
摘要翻译： 自适应均衡方法通过利用瞬时梯度向量的平均值来更新抽头系数，从而确保从接收数据生成的伪传输数据的可能性。
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2.发明授权Multiplier circuitry with improved storage and transfer of booth control coefficients 失效乘数电路，改进了展位控制系数的存储和传输
公开(公告)号：US5781462A
公开(公告)日：1998-07-14
申请号：US530580
申请日：1995-09-19
申请人： Kazuya Yamanaka , Sumitaka Takeuchi
发明人： Kazuya Yamanaka , Sumitaka Takeuchi
CPC分类号： G06F7/5338
摘要： It is an object of the present invention to simplify a multiplier so as to reduce the circuit scale of a digital filter which uses a large number of multipliers. Outputs of a Booth decoder 4 are stored in registers 5.sub.1 -5.sub.(n+1)/2 provided corresponding to partial product generating circuits 106.sub.1 -106.sub.(n+1)2. By providing control signals from the registers 5.sub.1 -5.sub.(n+1)/2 to the partial product generating circuits 106.sub.1 -106.sub.(n+1)/2, the Booth decoder 4 is made common. The number of Booth decoders which have conventionally been provided in a one-to-one correspondence with the partial product generating circuits can be reduced to one and the multiplier can be simplified.
摘要翻译： 本发明的目的是简化乘法器，以减少使用大量乘法器的数字滤波器的电路规模。 展位解码器4的输出被存储在对应于部分积产生电路1061-106（n + 1）2的寄存器51-5（n + 1）/ 2中。 通过从寄存器51-5（n + 1）/ 2向部分乘积产生电路1061-106（n + 1）/ 2提供控制信号，布斯解码器4是公共的。 传统上与部分积产生电路一一对应地提供的布斯解码器的数量可以减少到1个，乘法器可以简化。
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公开(公告)号：US5216424A
公开(公告)日：1993-06-01
申请号：US707145
申请日：1991-05-31
申请人： Hiroyuki Kouno , Sumitaka Takeuchi , Keisuke Okada
发明人： Hiroyuki Kouno , Sumitaka Takeuchi , Keisuke Okada
摘要： A binary data converter is adapted to convert a positive binary data into a negative binary data represented by a complement on two and vice verse. The conversion is effected as follows. A least significant bit of an inputted binary data is outputted as the least significant bit of the converted binary date as it is. With respect to bit signal other than the least significant bit, respective input bit signals less significant than the corresponding input bit signal are ORed. Depending on the result thereof, inverted or non-inverted signals of the corresponding input bit signals are outputted as the bit signals of the converted binary data. Therefore, carry delay is not generated, and thus the operation speed can be increased. Further, the simple circuit structures can reduce the number of required elements.
摘要翻译： 二进制数据转换器适于将正二进制数据转换成由二进制补码表示的负二进制数据。 转换如下进行。 输入的二进制数据的最低有效位作为转换的二进制日期的最低有效位被原样输出。 对于除了最低有效位之外的位信号，相对于相应的输入位信号而言，相对于输入位信号的有效值为“或”。 根据其结果，相应的输入位信号的反相或非反转信号作为转换的二进制数据的位信号被输出。 因此，不产生进位延迟，能够提高运转速度。 此外，简单的电路结构可以减少所需元件的数量。
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4.发明授权A/D converter comprising encoder portion having function of multiplying analogue input by digital input 失效A / D转换器包括具有通过数字输入将模拟输入相乘的编码器部分
公开(公告)号：US4903027A
公开(公告)日：1990-02-20
申请号：US159405
申请日：1988-02-11
申请人： Sumitaka Takeuchi , Keisuke Okada
发明人： Sumitaka Takeuchi , Keisuke Okada
摘要： An A/D converter of a serial-parallel comparison type has both multiplying functions of an analog input data and a digital input data. The analog input data V.sub.X is converted into a digital code I.sub.c corresponding to two more significant digits, by a first parallel comparing portion and a first determining circuit, and converted into a digital code I.sub.f corresponding to two less significant digits by a second parallel comparing portion and a second determining circuit. The digital codes I.sub.c and I.sub.f are alternately applied to a control circuit by a first selector circuit. Two more significant bits R.sub.c and two less significant bits R.sub.f of a 4-bit digital input data are respectively applied to a control signal generating circuit by a second selector circuit. Multiplications of R.sub.c I.sub.c, RfIc, R.sub.c I.sub.f and R.sub.f I.sub.f are serially performed within the time period of one conversion by the control signal generating circuit and the control circuit. The multiplied results are shifted four bits, two bits, two bits and 0 bits, respectively, and then, added to each other. As a result, the product of the analogue input data and the digital input data is calculated.
摘要翻译： 并行比较型的A / D转换器具有模拟输入数据和数字输入数据的乘法功能。 通过第一并行比较部分和第一确定电路将模拟输入数据VX转换成对应于两个有效数字的数字代码Ic，并且被转换成数字代码如果对应于由第二并行比较部分的两个较低有效数字 和第二确定电路。 数字代码Ic和If由第一选择器电路交替地施加到控制电路。 4位数字输入数据的两个有效位Rc和两个较低有效位Rf由第二选择器电路分别施加到控制信号发生电路。 RcIc，RfIc，RcIf和RfIf的乘法在控制信号发生电路和控制电路的一次转换的时间段内连续执行。 相乘的结果分别移位四位，两位，两位和0位，然后相加。 结果，计算模拟输入数据和数字输入数据的乘积。
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5.发明授权
公开(公告)号：US4896284A
公开(公告)日：1990-01-23
申请号：US226636
申请日：1988-08-01
摘要： A semiconductor integrated circuit so arranged that selection is made out of output signals of a decision circuit which determines the levels of analog values inputted as an object for multiplication and multiplication is carried out with respect to the selected signal and the digital value inputted as an object for multiplication, the result of the multiplication being added with the digital value as shifted to the higher position of specified bits, a multiplication result being thereby calculated with respect to the analog value and the digital value, whereby the required area of wiring connections is reasonably reduced and faster operation is assured.
摘要翻译： 一种半导体集成电路，其被配置为根据所选择的信号和作为对象输入的数字值，执行确定作为乘法和乘法对象输入的模拟值的电平的判定电路的输出信号的选择 为了乘法，乘法的结果被加上移动到指定位的较高位置的数字值，由此相对于模拟值和数字值计算乘法结果，由此所需的接线连接面积是合理的 减少和更快的操作得到保证。
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6.发明授权Absolute value comparing apparatus for comparing absolute values of data at high speed 失效绝对值比较装置，用于比较高速数据的绝对值
公开(公告)号：US5376915A
公开(公告)日：1994-12-27
申请号：US43710
申请日：1993-04-08
申请人： Sumitaka Takeuchi , Masao Ito
发明人： Sumitaka Takeuchi , Masao Ito
IPC分类号： G06F7/02
CPC分类号： G06F7/026
摘要： Disclosed is an absolute value comparator for comparing respective absolute values of sequentially applied two data. A decoder circuit sequentially converts the applied data into a plurality of bit signals in accordance with a predetermined rule. After a preceding conversion bit signal is once held in a register circuit, the held bit signal is inverted for each bit by an inversion circuit. Thus, a logic circuit receives a preceding inverted bit signal and a succeeding conversion bit signal and outputs an output signal B indicating the result of comparison. Since a full adder is unnecessary, a comparison between the absolute values of the applied data can be made at a high speed.
摘要翻译： 公开了一种用于比较顺序应用的两个数据的绝对值的绝对值比较器。 解码器电路根据预定规则顺序地将所施加的数据转换成多个比特信号。 在先前的转换位信号一旦被保持在寄存器电路中之后，所保持的位信号通过反相电路针对每个位反相。 因此，逻辑电路接收先前的反相位信号和后续转换位信号，并输出表示比较结果的输出信号B. 由于不需要全加器，所以可以高速地进行应用数据的绝对值之间的比较。
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公开(公告)号：US5583502A
公开(公告)日：1996-12-10
申请号：US263429
申请日：1994-06-21
申请人： Sumitaka Takeuchi , Toshio Kumamoto
发明人： Sumitaka Takeuchi , Toshio Kumamoto
摘要： There is disclosed an A-D converter testing circuit wherein exclusive-OR gates (13a, 13b) provide the exclusive-OR of the high-order bits (D.sub.1a, D.sub.1b) of the outputs of A-D converters (12a, 12b) and the exclusive-OR of the high-order bits (D.sub.1b, D.sub.1c) of the outputs of A-D converters (12b, 12c), respectively, and an OR gate (13c) provides the logical sum of the outputs of the both gates, which is "L" if all of the bits (D.sub.1a, D.sub.1b, D.sub.1c) are equal. A tri-state buffer (15a) receives the output of the OR gate (13c) at its control end and receives the bit (D.sub.1c) at its input. When all of the A-D converters are normal, all of the bits (D.sub.1a, D.sub.1b, D.sub.1c) are equal and are applied to the output of the tri-state buffer (15a). When one or some of the A-D converters are abnormal, the output of the tri-state buffer (15a) enters a high-impedance state. The A-D converter testing circuit, therefore, rapidly judges whether the A-D converters are defective or non-defective.
摘要翻译： 公开了一种AD转换器测试电路，其中异或门（13a，13b）提供AD转换器（12a，12b）的输出的高位（D1a，D1b）和异或 分别为AD转换器（12b，12c）的输出的高位（D1b，D1c）和或门（13c）提供两个门的输出的逻辑和，如果 所有位（D1a，D1b，D1c）相等。 三态缓冲器（15a）在其控制端接收或门（13c）的输出，并在其输入端接收位（D1c）。 当所有A-D转换器都正常时，所有位（D1a，D1b，D1c）都相等，并被施加到三态缓冲器（15a）的输出。 当一个或一些A-D转换器异常时，三态缓冲器（15a）的输出进入高阻抗状态。 因此，A-D转换器测试电路快速判断A-D转换器是有缺陷的还是无缺陷的。
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公开(公告)号：US5034912A
公开(公告)日：1991-07-23
申请号：US462379
申请日：1990-01-09
申请人： Sumitaka Takeuchi , Hiroyuki Kouno
发明人： Sumitaka Takeuchi , Hiroyuki Kouno
摘要： A multiplication processing circuit requiring no digital-analog converter includes a circuit for multiplying a digital multiplication coefficient by a digital multiplicand and outputting the result of multiplication as an analog current signal. The multiplication processing circuit includes a circuit for decoding the digital multiplication coefficient to generate one or a plurality of control signals, a circuit responsive to the digital multiplicand and to the generated control signal for generating a signal indicating, in decimal notation, the result of multiplication of the digital multiplication coefficient by the digital multiplicand, and a circuit for converting the signal indicating the result of multiplication into an analog current signal of a corresponding magnitude. Each of the control signals indicates at least one digital multiplication coefficient in decimal notation. The circuit for generating the signal indicative of the result of multiplication includes a circuit for logically processing, by logic gates, the control signal and the digital multiplicand. The logic gate circuit includes a circuit for detecting coincidence/non-coincidence between a pattern of the generated control signal and a bit pattern of the digital multiplicand, and a circuit responsive to the output of the detecting circuit for activating one of a plurality of possible signals indicating the results of multiplication.
摘要翻译： 不需要数模转换器的乘法处理电路包括用于将数字乘法系数乘以数字乘法器并输出乘法结果作为模拟电流信号的电路。 乘法处理电路包括用于解码数字乘法系数以产生一个或多个控制信号的电路，响应于数字被乘数的电路和产生的控制信号，用于产生以十进制格式表示乘法结果的信号 数字乘法器的数字乘法系数，以及用于将表示乘法结果的信号转换成相应幅度的模拟电流信号的电路。 每个控制信号以十进制形式表示至少一个数字乘法系数。 用于产生指示乘法结果的信号的电路包括逻辑门逻辑处理控制信号和数字被乘数的电路。 逻辑门电路包括用于检测所产生的控制信号的模式与数字被乘数的位模式之间的符合/非重合的电路，以及响应于检测电路的输出的电路，用于激活多个可能的 指示乘法结果的信号。
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公开(公告)号：US4918453A
公开(公告)日：1990-04-17
申请号：US181338
申请日：1988-04-14
摘要： A semiconductor integrated circuit which is comprised of the following; a plurality of comparators which respectively compare analog values inputted for multiplication with individual reference voltages respectively, multiplication means which controls values outputted from those plural comparators by applying signals corresponding to digital values inputted for multiplication and outputs the product of the values outputted from those plural comparators and the digital values, and a complement operation circuit which converts the value outputted from multiplication means into complement when the digital value is negative.
摘要翻译： 一种半导体集成电路，由以下组成： 多个比较器分别比较输入的各个参考电压与各个参考电压相乘所输入的乘法运算的乘法运算装置，通过应用与输入乘法运算的数字值对应的信号来控制从这些多个比较器输出的值，并输出从这些多个比较器输出的值的乘积 和数字值，以及当数字值为负时将从乘法装置输出的值转换为补码的补码运算电路。
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公开(公告)号：US4866443A
公开(公告)日：1989-09-12
申请号：US111047
申请日：1987-10-21
申请人： Keisuke Okada , Sumitaka Takeuchi
发明人： Keisuke Okada , Sumitaka Takeuchi
摘要： A semiconductor integrated circuit includes a plurality of comparators for comparing an analog input with reference voltage or voltages, holding means for holding a digital value, and control means for controlling the outputs of the plurality of comparators by a control signal responsive to the digital value to output the multiplication result of the output values of the plurality of comparators and the digital value. Thus, the integrated circuit can construct a circuit having functions of an A/D converter and a multiplier on one chip.
摘要翻译： 半导体集成电路包括用于将模拟输入与参考电压或电压进行比较的多个比较器，用于保持数字值的保持装置和用于通过响应于数字值的控制信号来控制多个比较器的输出的控制装置 输出多个比较器的输出值的相乘结果和数字值。 因此，集成电路可以在一个芯片上构造具有A / D转换器和乘法器的功能的电路。
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