公开(公告)号：US20130052760A1

公开(公告)日：2013-02-28

申请号：US13545385

申请日：2012-07-10

申请人： Sung-Dong CHO ,  Yeong-Lyeol PARK ,  Min-Seung YOON

发明人： Sung-Dong CHO ,  Yeong-Lyeol PARK ,  Min-Seung YOON

IPC分类号： H01L21/66

CPC分类号： H01L22/14 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/31717 ,  G01R31/318513 ,  H01L22/32 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/81

摘要： In an exemplary method of inspecting a stack chip package, a first chip is prepared. The first chip includes a through-silicon via, first pad electrodes connected to the through-silicon via and probe pad electrodes connected to the through-silicon via. A testing chip is prepared. The testing chip includes second pad electrodes that are arranged to correspond with the first pad electrodes. The testing chip is temporarily adhered to the first chip such that the second pad electrodes are electrically connected to the first pad electrode respectively, to form a stack structure wherein the probe pad electrodes are exposed to for testing. An electrical signal is applied to the exposed probe pad electrodes to test the through-silicon via included in the first chip.

摘要翻译： 在检查堆叠芯片封装的示例性方法中，准备第一芯片。 第一芯片包括穿硅通孔，连接到穿硅通孔的第一焊盘电极和连接到穿硅通孔的探针焊盘电极。 准备了一个测试芯片。 测试芯片包括被布置为与第一焊盘电极对应的第二焊盘电极。 将测试芯片临时粘附到第一芯片，使得第二焊盘电极分别电连接到第一焊盘电极，以形成其中探针焊盘电极暴露以进行测试的堆叠结构。 将电信号施加到暴露的探针焊盘电极，以测试包括在第一芯片中的穿硅通孔。

公开(公告)号：US20160233155A1

公开(公告)日：2016-08-11

申请号：US15130904

申请日：2016-04-15

申请人： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

发明人： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

摘要翻译： 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。

公开(公告)号：US20120133048A1

公开(公告)日：2012-05-31

申请号：US13235369

申请日：2011-09-17

申请人： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

发明人： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

IPC分类号： H01L23/48

CPC分类号： H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

摘要翻译： 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。