利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.027 秒)

    Dual gate cascade amplifier
    1.
    发明申请
    Dual gate cascade amplifier 失效
    双门级联放大器

    公开(公告)号：US20050073366A1

    公开(公告)日：2005-04-07

    申请号：US10956082

    申请日：2004-10-04

    申请人： Sung-jae Jung ,  Hoon-tae Kim ,  Yun-seong Eo ,  Kwang-du Lee ,  Sang-yoon Jeon

    发明人： Sung-jae Jung ,  Hoon-tae Kim ,  Yun-seong Eo ,  Kwang-du Lee ,  Sang-yoon Jeon

    IPC分类号： H01L27/02 ,  H01L27/07 ,  H03F1/22

    CPC分类号： H03F1/223 ,  H01L27/0207 ,  H01L27/0705

    摘要： A dual gate cascade amplifier includes a first transistor and a second transistor electrically connected in series, the second transistor including a first parallel transistor and a second parallel transistor, the first parallel transistor and the second parallel transistor being electrically connected in parallel, a first channel electrically connecting a first end channel region of the first transistor and a second end channel region, wherein one of the first or second end channel regions is a source and the other of the first or second end channel regions is a drain, the second end channel region being a common end channel region shared by the first and second parallel transistors, and a second channel electrically connected to the second end channel region and extending away from the first transistor.

    摘要翻译： 双栅级联放大器包括串联电连接的第一晶体管和第二晶体管，第二晶体管包括第一并联晶体管和第二并联晶体管，第一并联晶体管和第二并联晶体管并联电连接，第一沟道 电连接第一晶体管的第一端部沟道区域和第二端部沟道区域，其中第一或第二端部沟道区域之一是源极，并且第一或第二端部沟道区域中的另一个是漏极，第二端部通道 区域是由第一和第二并联晶体管共享的公共末端通道区域，以及电连接到第二端部通道区域并远离第一晶体管延伸的第二通道。

    Dual gate cascade amplifier
    2.
    发明授权
    Dual gate cascade amplifier 失效
    双门级联放大器

    公开(公告)号：US07199669B2

    公开(公告)日：2007-04-03

    申请号：US10956082

    申请日：2004-10-04

    申请人： Sung-jae Jung ,  Hoon-tae Kim ,  Yun-seong Eo ,  Kwang-du Lee ,  Sang-yoon Jeon

    发明人： Sung-jae Jung ,  Hoon-tae Kim ,  Yun-seong Eo ,  Kwang-du Lee ,  Sang-yoon Jeon

    IPC分类号： H03F3/04

    CPC分类号： H03F1/223 ,  H01L27/0207 ,  H01L27/0705

    摘要： A dual gate cascade amplifier includes a first transistor and a second transistor electrically connected in series, the second transistor including a first parallel transistor and a second parallel transistor, the first parallel transistor and the second parallel transistor being electrically connected in parallel, a first channel electrically connecting a first end channel region of the first transistor and a second end channel region, wherein one of the first or second end channel regions is a source and the other of the first or second end channel regions is a drain, the second end channel region being a common end channel region shared by the first and second parallel transistors, and a second channel electrically connected to the second end channel region and extending away from the first transistor.

    摘要翻译： 双栅级联放大器包括串联电连接的第一晶体管和第二晶体管，第二晶体管包括第一并联晶体管和第二并联晶体管，第一并联晶体管和第二并联晶体管并联电连接，第一沟道 电连接第一晶体管的第一端部沟道区域和第二端部沟道区域，其中第一或第二端部沟道区域之一是源极，并且第一或第二端部沟道区域中的另一个是漏极，第二端部通道 区域是由第一和第二并联晶体管共享的公共末端通道区域，以及电连接到第二端部通道区域并远离第一晶体管延伸的第二通道。

    Integrated circuit having integrated inductors
    3.
    发明授权
    Integrated circuit having integrated inductors 有权
    具有集成电感器的集成电路

    公开(公告)号：US07525407B2

    公开(公告)日：2009-04-28

    申请号：US11353966

    申请日：2006-02-15

    申请人： Kwang-du Lee ,  Yun-seong Eo ,  Hee-mun Bang ,  Seong-soo Lee ,  Sung-jae Jung ,  Heung-bae Lee

    发明人： Kwang-du Lee ,  Yun-seong Eo ,  Hee-mun Bang ,  Seong-soo Lee ,  Sung-jae Jung ,  Heung-bae Lee

    IPC分类号： H01F5/00

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An integrated circuit having integrated inductors includes at least one pair of transistors, and at least one inductor group which includes a pair of inductors coupled to the at least one pair of the transistor, respectively. The pair of the inductors form a spiral shape on a plane and the inductors arranged symmetrically to each other. Magnetic fluxes, which are generated by current flows along the inductors of the at least one inductor group, are formed in a direction to mutually intensify the magnetic fluxes according to differential signals applied to the at least one transistors from outside. Accordingly, high inductance and high quality factor can be attained owing to the positive magnetic coupling of the inductors.

    摘要翻译： 具有集成电感器的集成电路包括至少一对晶体管，以及至少一个电感器组，其包括分别耦合到至少一对晶体管的一对电感器。 一对电感器在平面上形成螺旋形状，并且电感器彼此对称布置。 通过沿着至少一个电感器组的电感器流动的电流产生的磁通量根据从外部施加到至少一个晶体管的差分信号沿相互强化磁通量的方向形成。 因此，由于电感器的正磁耦合，可以获得高电感和高品质因数。

    MIM capacitor including ground shield layer
    5.
    发明申请
    MIM capacitor including ground shield layer 审中-公开
    MIM电容器包括接地屏蔽层

    公开(公告)号：US20060197133A1

    公开(公告)日：2006-09-07

    申请号：US11360585

    申请日：2006-02-24

    申请人： Sung-jae Jung ,  Sang-yoon Jeon ,  Hee-mun Bang ,  Kwang-du Lee ,  Heung-bae Lee

    发明人： Sung-jae Jung ,  Sang-yoon Jeon ,  Hee-mun Bang ,  Kwang-du Lee ,  Heung-bae Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L23/5225 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An MIM capacitor includes a substrate, a capacitor part having a structure in which a bottom electrode, a dielectric layer and a top electrode are laminated in order, and a ground shield layer formed between the bottom electrode of the capacitor part and the substrate and connected to a predetermined ground terminal. The ground shield layer may be formed of metal or polysilicon, or a layer doped with impurities having a valence of three or five. Also, the ground shield layer has a predetermined patterned structure. Thus, it is possible to minimize power loss due to the substrate.

    摘要翻译： MIM电容器包括基板，具有依次层叠底部电极，电介质层和顶部电极的结构的电容器部分，以及形成在电容器部分的底部电极和基板之间的接地屏蔽层，并连接 到预定的接地端子。 接地屏蔽层可以由金属或多晶硅形成，或者掺杂有三价或五价杂质的层。 此外，接地屏蔽层具有预定的图案结构。 因此，可以最小化由于衬底引起的功率损耗。

    Complementary metal oxide semiconductor voltage controlled oscillator
    8.
    发明申请
    Complementary metal oxide semiconductor voltage controlled oscillator 有权
    互补金属氧化物半导体压控振荡器

    公开(公告)号：US20060197621A1

    公开(公告)日：2006-09-07

    申请号：US11355976

    申请日：2006-02-17

    申请人： Sang-yoon Jeon ,  Heung-bae Lee ,  Sung-jae Jung

    发明人： Sang-yoon Jeon ,  Heung-bae Lee ,  Sung-jae Jung

    IPC分类号： H03B5/08

    CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B2200/0062

    摘要： A complementary metal oxide semiconductor voltage controlled oscillator is provided. The voltage controlled oscillator includes an LC tank which is supplied with a power supply voltage, the LC tank oscillating at a certain frequency; a negative resistor including first and second N-channel metal oxide semiconductor field effect transistors (NMOS FETs) to sustain the oscillation of the LC tank; a direct current block to remove a direct current component from the power supply voltage; an alternating current block to apply an alternating current voltage to the gates of the first and second NMOS FETs; a first current mirror including third and fourth NMOS FETs and allowing a current to symmetrically flow in the voltage controlled oscillator, a drain and the gate of the third NMOS FET being connected to a reference voltage supply; and the reference voltage supply applying a direct current voltage to the first current mirror.

    摘要翻译： 提供了互补金属氧化物半导体压控振荡器。 压控振荡器包括一个供应电源电压的LC箱，LC箱以一定的频率振荡; 包括第一和第二N沟道金属氧化物半导体场效应晶体管（NMOS FET）的负电阻器，以维持LC箱的振荡; 直流电流块，用于从电源电压中去除直流分量; 交流电流块，用于向第一和第二NMOS FET的栅极施加交流电压; 第一电流镜包括第三和第四NMOS FET，并允许电流在压控振荡器中对称地流动，第三NMOS FET的漏极和栅极连接到参考电压源; 并且所述参考电压电源向所述第一电流镜施加直流电压。

    NxN multiple-input multiple-output transceiver
    9.
    发明授权
    NxN multiple-input multiple-output transceiver 失效
    NxN多输入多输出收发器

    公开(公告)号：US07848435B2

    公开(公告)日：2010-12-07

    申请号：US11543120

    申请日：2006-10-05

    申请人： Sang-yoon Jeon ,  Hee-mun Bang ,  Sung-jae Jung ,  Heung-bae Lee

    发明人： Sang-yoon Jeon ,  Hee-mun Bang ,  Sung-jae Jung ,  Heung-bae Lee

    IPC分类号： H04L1/02

    CPC分类号： H04B7/0413 ,  H04L1/06

    摘要： An N×N multiple-input multiple-output (MIMO) transceiver is provided. The transceiver includes a plurality of transceivers, each including at least one transceiver circuit; an oscillation unit which is configured to generate a differential signal which is supplied to the at least one transceiver circuit; a plurality of buffers, which are mounted in a bypass line between the at least one transceiver circuit and the oscillation unit and are configured to amplify and bypass the differential signal or input and amplify the differential signal; and a buffer control unit which is configured to control the plurality of buffers to bypass or input the differential signal.

    摘要翻译： 提供了一种N×N多输入多输出（MIMO）收发器。 收发器包括多个收发器，每个收发器包括至少一个收发器电路; 振荡单元，被配置为生成提供给所述至少一个收发器电路的差分信号; 多个缓冲器，其安装在所述至少一个收发器电路和所述振荡单元之间的旁路线路中，并且被配置为放大和旁路所述差分信号或者输入和放大所述差分信号; 以及缓冲器控制单元，其被配置为控制所述多个缓冲器来旁路或输入所述差分信号。