公开(公告)号：US20180158526A1

公开(公告)日：2018-06-07

申请号：US15826031

申请日：2017-11-29

申请人： Sung-woo KIM ,  Jae-kyu LEE ,  Ki-seok SUH ,  Hyeong-sun HONG ,  Yoo-sang HWANG ,  Gwan-hyeob KOH

发明人： Sung-woo KIM ,  Jae-kyu LEE ,  Ki-seok SUH ,  Hyeong-sun HONG ,  Yoo-sang HWANG ,  Gwan-hyeob KOH

IPC分类号： G11C14/00 ,  H01L27/22 ,  H01L29/08 ,  H01L27/108 ,  H01L23/528 ,  H01L29/423 ,  H01L45/00 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L27/24

摘要： An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

公开(公告)号：US20170053688A1

公开(公告)日：2017-02-23

申请号：US15153866

申请日：2016-05-13

申请人： Bo-young SEO ,  Yong-seok CHUNG ,  Gwan-hyeob KOH ,  Yong-kyu LEE

发明人： Bo-young SEO ,  Yong-seok CHUNG ,  Gwan-hyeob KOH ,  Yong-kyu LEE

IPC分类号： G11C11/16

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  H01L27/228 ,  H01L43/08

摘要： A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.

摘要翻译： 电阻式存储装置包括具有多个存储单元的存储单元阵列和第一接地开关。 多个存储单元被布置成多行和多列，并且多个存储单元的第一列中的每个存储单元连接在第一位线和第一源极线之间。 第一接地开关与第一源极线并联连接，并且第一接地开关被配置为选择性地提供从第一位线到接地的第一电流路径，通过多个存储单元的第一列中的选定存储单元， 第一个源行，当前路径仅遍历第一个源行的一部分。